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Commit Graph

167 Commits

Author SHA1 Message Date
Megan Wachs
d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00
Wesley W. Terpstra
b4188ee625 axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
Megan Wachs
d67738204f Interrupts: Less Pessimistic Synchronization (#714)
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Henry Cook
3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex 2017-04-27 18:17:09 -07:00
Wesley W. Terpstra
b4d17c76d1 coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00
Megan Wachs
df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655)
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
Megan Wachs
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce Debug Controls (#639)
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Wesley W. Terpstra
a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
Megan Wachs
42ca597478 debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Megan Wachs
08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616)
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Wesley W. Terpstra
537274b645 coreplex: move buffers inside the coreplex
This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078 rename l2FrontendBus as fsb, expose bsb 2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610)
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00
Andrew Waterman
3ea822c2cf Make blocking L1 D$ the default
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
Wesley W. Terpstra
19eb9b6906 l1tol2: put a flow Q on the exits (#606)
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
Wesley W. Terpstra
81d717e82f coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00
Andrew Waterman
db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Wesley W. Terpstra
1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
4535de2669 rocket: use diplomatic interrupts
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550)
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
Wesley W. Terpstra
d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra
b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
2017-02-03 17:19:21 -08:00
Wesley W. Terpstra
93b2fa197e Artefact output (#545)
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
Wesley W. Terpstra
280af9684b BankedL2Config: use the same LazyModule for all L2 banks
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
2017-01-30 14:02:59 -08:00
Wesley W. Terpstra
24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
Wesley W. Terpstra
03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
Wesley W. Terpstra
3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager
This lets smart caches exclude the sets that are filtered.
2017-01-21 13:23:07 -08:00
Wesley W. Terpstra
dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
Wesley W. Terpstra
3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Henry Cook
e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Henry Cook
9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513)
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00