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rocket-chip/src/main/scala/coreplex
2017-04-19 16:16:05 -07:00
..
BaseCoreplex.scala rocket: use diplomatic interrupts 2017-03-02 21:19:23 -08:00
Configs.scala coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00
Coreplex.scala rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
CoreplexNetwork.scala soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
RISCVPlatform.scala debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
RocketTiles.scala coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00