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riscv
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rocket-chip
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a2fc51d65e
rocket-chip
/
src
/
main
/
scala
/
coreplex
History
Wesley W. Terpstra
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
..
BaseCoreplex.scala
rocket: use diplomatic interrupts
2017-03-02 21:19:23 -08:00
Configs.scala
Make blocking L1 D$ the default
2017-03-24 16:39:52 -07:00
Coreplex.scala
rocketchip: pass variable l1tol2 connections into coreplex
2017-01-29 11:18:36 -08:00
CoreplexNetwork.scala
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
RISCVPlatform.scala
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
RocketTiles.scala
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00