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rocket-chip/src/main/scala/coreplex
Megan Wachs 42ca597478 debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
..
BaseCoreplex.scala rocket: use diplomatic interrupts 2017-03-02 21:19:23 -08:00
Configs.scala debug: Breaking change until FESVR is updated as well. 2017-03-27 21:19:08 -07:00
Coreplex.scala rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
CoreplexNetwork.scala coreplex: move buffers inside the coreplex 2017-03-24 22:54:48 -07:00
RISCVPlatform.scala debug: Breaking change until FESVR is updated as well. 2017-03-27 21:19:08 -07:00
RocketTiles.scala debug: Breaking change until FESVR is updated as well. 2017-03-27 21:19:08 -07:00