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Commit Graph

67 Commits

Author SHA1 Message Date
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
8550582f84 remove redundant verilator rule 2016-09-14 20:31:17 -07:00
a304695ffd Add firrtl and verilog Makefile targets to vsim 2016-09-14 20:29:59 -07:00
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
2572cd3f7c Add missing dependency 2016-09-14 11:50:28 -07:00
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
6be569be9f Turn on the inferRW Firrtl pass
Without this, all of the memories wind up as two-ported.
2016-09-07 15:27:26 -07:00
92718e4b61 fix null statement in vsli_mem_gen ala firrtl#264 (#252) 2016-09-07 11:04:36 -07:00
e95fe646a3 mem_gen failure doesn't create the target 2016-09-06 16:29:29 -07:00
48098f5e2d Bump FIRRTL to instantiate Sequential Memory Macros 2016-09-06 14:48:28 -07:00
1fec9807f6 allow override of vlsi_mem_gen script 2016-09-06 14:44:12 -07:00
4a7972be31 connect testharness components via member functions (#236)
to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
08089f695d allow configuration to be in separate project from test harness 2016-09-01 10:28:07 -07:00
a19bd6de96 Get in line with FIRRTL randomization flag changes (#231) 2016-08-29 12:29:01 -07:00
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
4f388add67 More accurate conditional include of generated .d make fragment (#222) 2016-08-25 14:42:04 -07:00
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00
a39a0c0ec4 .prm is output of chisel stage, not firrtl stage 2016-06-28 17:34:37 -07:00
87a4858aa6 Exit from testbench, not C code
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
568bfa6c50 Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
e6c4372332 Fix "make run-asm-tests" for Chisel 3
This was just a missing Makefrag-verilog dependency (the .d file).
2016-06-06 21:36:55 -07:00
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
18ffe7b1ec don't use +verbose in vsim .run rule 2016-05-04 23:01:14 -07:00
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
This reverts commit 5378f79b50.
2016-03-30 19:06:32 -07:00
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
cddfdf0929 Add CHISEL_VERSION make argument
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
e0d849fec5 Fix zscale testing
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
07f0e6be94 Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
1e772daeea no spaces in Makefrag 2015-11-05 16:42:05 -08:00
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
83df4bcc35 Fixed run-bmark-tests make target in vsim 2015-09-09 22:37:47 -07:00
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00