Howard Mao
27745204eb
ErrorSlave returns response of correct length for reads
2015-09-22 09:42:57 -07:00
Andrew Waterman
e72e5a34b5
Fix storage of SP values in DP registers
...
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s. This meant that an FSD + FLD of that register
would not restore the value properly.
Also, minor code cleanup.
2015-09-21 12:20:44 -07:00
Andrew Waterman
c6bcc832a1
Chisel3: Don't use Vec.fill for IOs
2015-09-20 13:43:56 -07:00
Andrew Waterman
fd58c52250
Update to latest chisel
2015-09-20 13:37:53 -07:00
Howard Mao
4db6124b2a
NASTIErrorSlave should print address
2015-09-18 09:42:41 -07:00
Howard Mao
8b2341b1b1
use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter
2015-09-18 09:41:37 -07:00
Colin Schmidt
6f85ed191e
Add rocketchip_addons to the list of chisel srcs requiring rebuild
2015-09-16 12:28:03 -07:00
Colin Schmidt
7ecb936bf5
Remove -j from "make run-bmark-tests" in travis
...
+currently causes inconsistency in build success
+unclear what root cause is
2015-09-16 12:27:05 -07:00
Scott Beamer
de81762f7c
faster and more conservative float_fix
2015-09-15 17:19:29 -07:00
Scott Beamer
7e25b1ce03
cleaner/faster comlog without linear search
2015-09-15 17:19:29 -07:00
Christopher Celio
76bf1da310
[commitlog] zero-extend SP write-back values
2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c
[commitlog] don't print out writebacks to x0
2015-09-15 16:47:26 -07:00
Christopher Celio
e22bf02a80
[commitlog] CSR's cycle optionally set to instret
...
- Allows debugging Rocket against Spike by having timer interrupts
occur in the same place in the instruction stream for both.
2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262
[commitlog] Added privilege-level to output
2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8
[commitlog] Fix sp/dp bug in FPU writeback
2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857
[commitlog] Added FP instructions to the commitlog
2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c
[commitlog] Initial commit log for integer working
2015-09-15 15:59:03 -07:00
Christopher Celio
754c47bdd1
Removed "make debug" test from travis
...
- currently causes gcc4.8 to crash
- likely due to high memory requirements in compiling generated c++
code for debug/vcd output
2015-09-14 15:45:50 -07:00
Colin Schmidt
d355d81633
regression script bump for new torture that can produce waveforms
2015-09-14 13:00:54 -07:00
Howard Mao
bd536d8832
make HTIFModuleIO an anonymous bundle
2015-09-14 12:58:44 -07:00
Howard Mao
9d89d2a558
get rid of MemIO -> TileLink converters
2015-09-14 12:58:44 -07:00
Howard Mao
f9965648f2
fix up some things in tilelink.scala
2015-09-14 12:57:54 -07:00
Howard Mao
64717706a9
get rid of non-NASTI RTC module
2015-09-14 12:57:54 -07:00
Howard Mao
6ee6ea4f1e
use Put/Get/PutBlock/GetBlock constructors in broadcast hub
2015-09-14 12:57:54 -07:00
Howard Mao
ae3d96013a
make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper
2015-09-14 12:57:54 -07:00
Howard Mao
21f96f382c
split off SCR functionality from HTIF
2015-09-14 12:57:54 -07:00
Howard Mao
bdc6972a8d
separate RTC updates from HTIF
2015-09-14 12:56:44 -07:00
Howard Mao
24f3fac90a
fix broadcast hub and TL -> NASTI converter to support subblock operations
2015-09-14 12:56:44 -07:00
Scott Beamer
3eed7ff238
make float_fix more conservative with replacement
2015-09-12 11:00:00 -07:00
Scott Beamer
a12cd13190
tool to unrecode single floats from commit logs
2015-09-11 20:19:18 -07:00
Christopher Celio
c2344ee2bc
Added generated-src-debug to make clean target
2015-09-11 19:07:33 -07:00
Christopher Celio
c9d89226fb
Generated *.d file of tests now kept in order
...
-Changed Set to LinkedHashSet in Testing.scala
2015-09-11 18:36:04 -07:00
Christopher Celio
c8a7deb950
Added a commitlog post-processor for Rocket
...
- Useful for taking Rocket's out-of-order writebacks and generating an
in-order commit log.
- Resulting commit log can be diffed against Spike's commit log.
2015-09-11 16:06:01 -07:00
Andrew Waterman
78b2e947de
Chisel3 compatibility fixes
2015-09-11 15:43:07 -07:00
Andrew Waterman
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
Howard Mao
4c3c3c630e
add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len
2015-09-10 17:55:10 -07:00
Christopher Celio
17e971bbfa
Add emulator "make debug" and "-j" to travis
2015-09-10 17:34:16 -07:00
Howard Mao
6387d31c62
add comments and small fixes for NASTI and SMI
2015-09-10 17:33:48 -07:00
Howard Mao
8a8d52da4f
add convenient constructors for NASTI channels
2015-09-10 17:33:31 -07:00
Christopher Celio
d9a2162472
Bump Chisel
2015-09-10 17:26:41 -07:00
Christopher Celio
8f71c4da2d
Reintroduced multiple emulator backend directories
...
Fixes a "make -j" concurrency bug due to deleting files that another
parallel rule depends on.
2015-09-10 17:14:23 -07:00
Christopher Celio
83df4bcc35
Fixed run-bmark-tests make target in vsim
2015-09-09 22:37:47 -07:00
Colin Schmidt
af7336ef8b
blacklist private branches from travis
2015-09-08 15:13:38 -07:00
Colin Schmidt
d292b6cb13
don't connect rocc-fpu-port without rocc accel
2015-09-08 14:44:12 -07:00
Andrew Waterman
d08b75c472
Merge pull request #15 from ucb-bar/fix_disasm_garbage
...
If you don't have spike-disasm in your path, your path is dumped
2015-09-03 17:55:31 -07:00
Ben Keller
8e9c15c10d
If you don't have spike-disasm in your path, your path is dumped
...
to stdout by this line every time you do anything in the entire repo.
2015-09-03 15:36:11 -07:00
Christopher Celio
e6b6ff5a1d
Update README.md
...
Corrected PublicConfigs.scala -> Configs.scala
2015-09-02 22:55:53 -07:00
Howard Mao
ede1ada053
Add converters and utilities for simpler peripheral interface (SMI)
2015-09-01 14:00:45 -07:00
Howard Mao
75ec7529af
implement NASTI Interconnect generating from configuration address map
2015-09-01 14:00:45 -07:00
Howard Mao
b046c57284
make NASTI -> MemIO converter compliant to AXI4 spec
2015-09-01 11:17:38 -07:00
