riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,360 Commits 1 Branch 0 Tags
bab0b99d7ab5340455a3d4bd87fea4b7b61cdf64
Commit Graph
5360 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Henry CookandGitHub bab0b99d7a Merge pull request #1131 from freechipsproject/fix-dcache-tag-ecc-error-under-flush 
Avoid data corruption under correctable tag error during flush
 2017-11-30 12:27:15 -08:00
Andrew Waterman 890528c641 Avoid data corruption under correctable tag error during flush 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 16:09:44 -08:00
Andrew Waterman 34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" 
This reverts commit 44eb4d12b5.
 2017-11-29 16:09:30 -08:00
Andrew WatermanandHenry Cook 44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 09:42:00 -08:00
Megan WachsandGitHub 9d489c6dcd Merge pull request #1128 from freechipsproject/chisel_527_fixed 
debug: Remove workaround for Chisel 3 #527
 2017-11-27 16:53:02 -08:00
Megan Wachs f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Andrew WatermanandGitHub 5155eb6059 Don't emit writeback state machine logic for scratchpad (#1127) 
Firrtl can't DCE it because it would require analyzing the state machine.
 2017-11-22 18:40:02 -06:00
Wesley W. TerpstraandGitHub a8d573beeb Merge pull request #1123 from freechipsproject/dts-global 
DTS global
 2017-11-20 19:09:03 -08:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra 3b299397db diplomacy: bind resources to outer-most binding 
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra 44f99cd9a5 diplomacy: eliminate redundant bindings 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
Andrew WatermanandGitHub 39f1acfd34 Merge pull request #1122 from freechipsproject/fix-itim 
Fix ITIM deallocation during I$ refill causing data corruption
 2017-11-20 15:08:25 -08:00
Yunsup Lee a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00
Andrew Waterman 5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption 
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db066303b.
 2017-11-20 12:30:40 -08:00
Andrew Waterman 66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" 
This reverts commit 3db066303b.
 2017-11-20 12:26:04 -08:00
Wesley W. TerpstraandGitHub 342dd82fcf Merge pull request #1119 from freechipsproject/verify-blocker-width 
Verify blocker width
 2017-11-18 15:45:24 -08:00
Wesley W. Terpstra ec809483b0 BusBypass: assert fail if the widths of the two slaves do not match 2017-11-18 14:37:27 -08:00
Wesley W. Terpstra c475c78c2f BusBlocker: don't provide an (incorrect) default value for width 2017-11-18 14:33:00 -08:00
Wesley W. Terpstra 7a1937242a coreplex: provide correct bus-width for ITIM blockers 2017-11-18 14:32:37 -08:00
Henry CookandGitHub 9e0c26f855 Merge pull request #1118 from freechipsproject/basic-bus-blocker-3 
tile: bus blocker needs to know width
 2017-11-17 21:57:20 -08:00
Megan WachsandGitHub 6229c7b1ff Merge pull request #1117 from freechipsproject/debug_test_tools 
debug: bump riscv-tools/riscv-tests/debug for Priv test fixes
 2017-11-17 20:54:41 -08:00
Henry Cook f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry CookandGitHub b625e68360 tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Megan Wachs 68c5981363 debug: bump riscv-tools/riscv-tests/debug for Priv test fixes 2017-11-17 16:06:50 -08:00
Megan WachsandGitHub e7704f46c8 Add some add'l debug features (#1112) 
* debug: Update macros from spec

* debug: some corrections in the auto-generated files

* debug: update renamed fields

* Debug: implement the implicit ebreak option for small program buffers

* debug: clean up some unused code and add more require() explanations

* debug: make implicit ebreak false

* debug: Add the havereset/haveresetack functionality

* debug: program buffer can still be 16 even if there is an implicit ebreak
 2017-11-16 17:14:41 -08:00
Gleb GagarinandGitHub acc8c2bbb3 Merge pull request #1113 from freechipsproject/bump_spike 
Bumped riscv-tools/riscv-isa-sim
 2017-11-16 11:19:53 -08:00
Gleb Gagarin fca2e7f9aa Bumped riscv-tools/riscv-isa-sim 2017-11-15 19:15:47 -08:00
Wesley W. TerpstraandGitHub 61ef560c75 tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111) 2017-11-14 17:49:10 -08:00
Wesley W. TerpstraandGitHub 8b79f0394e Merge pull request #1105 from freechipsproject/axi4-xbar 
axi4: add an Xbar
 2017-11-14 16:18:23 -08:00
Wesley W. TerpstraandGitHub 509a48c9c9 TLToAXI4: block TL early source re-use before it goes to AXI4 (#1110) 
This is a follow-up to PR #1108.

Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
 2017-11-14 16:08:43 -08:00
Wesley W. Terpstra e370934c50 AXI4Xbar: reduce number of special cases 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 9004ecdf25 unittest: include AXI4Xbar in regression 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 5875017956 axi4: add an Xbar 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 72c89f7e30 axi4: add a Filter suitable for manipulating test visibility 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra bfc0ba679a axi4: add a Delayer for unit tests 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 1902ba063a Filter: can claim to be out-of-order when you are not 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 58a93e2100 AXI4SRAM: handy helper object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 353ddffc11 RAMModel: add a convenience object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Wesley W. TerpstraandGitHub 147fad6387 Fix AXI4 FIFO ordering for masters with early source reuse (#1108) 
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
 2017-11-13 20:32:09 -08:00
Henry CookandGitHub 7098ebf439 rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Andrew WatermanandGitHub b317735319 Merge pull request #1106 from freechipsproject/bump-tools 
bump tools for .align 2 fix in riscv-tests
 2017-11-11 23:36:28 -08:00
Andrew Waterman f0a0687589 bump tools for .align 2 fix in riscv-tests 2017-11-11 19:13:59 -08:00
Wesley W. TerpstraandGitHub 0cfa801bfc coreplex: allow MMIO to be misaligned (#1103) 2017-11-10 15:12:28 -08:00
Wesley W. TerpstraandGitHub a061b16ee3 coreplex: fix typo (#1104) 2017-11-10 15:11:56 -08:00
Andrew WatermanandGitHub 35d377d122 Merge pull request #1100 from freechipsproject/disable-local-amos 
Provide option to support AMOs only on I/O, not DTIM/D$
 2017-11-09 21:20:55 -08:00
Andrew Waterman 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew WatermanandGitHub efdb418559 Merge pull request #1098 from freechipsproject/frontend 
Frontend improvements
 2017-11-09 17:44:38 -08:00
Wesley W. TerpstraandGitHub 50ce3f5086 Merge pull request #1097 from freechipsproject/itim-error 
More ITIM error-handling improvements
 2017-11-09 00:17:48 -08:00