b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
53360f4c2c
Disable U-mode by default unless S-mode is present
2016-10-08 21:29:40 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
968851f7e3
Default to configurable priorities
...
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
e928b741ce
Default mtvec=0, not None
...
Setting it to None was a mistake. It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
2016-09-29 13:52:41 -07:00
c45cc76cef
Get rid of remaining MemIO code
...
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
7d6fb950b6
Give TileLink IDs more sensible names
...
* Outermost -> MCtoEdge
* MMIO_Outermost -> MMIOtoEdge
Then the corresponding parameters objects are
* L1toL2 -> innerParams
* L2toMC -> outerMemParams
* L2toMMIO -> outerMMIOParams
* MCtoEdge -> edgeMemParams
* MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
8a55521b01
move memory width adapter from coreplex to periphery
2016-09-27 12:48:01 -07:00
201e247f73
Factor coreplex IO connection into separate trait ( #350 )
...
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.
The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
803739a95c
Make sure coreplex mmio's TLId is correct (thanks to zizztux)
2016-09-26 17:28:21 -07:00
1e54820f8c
Merge remote-tracking branch 'origin/master' into unittest-config
2016-09-22 16:03:51 -07:00
47c5d1a992
[WIP] Move RocketTestSuite generation into RocketchipGenerator
2016-09-22 14:31:45 -07:00
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
d2df6397cd
rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
fd5e00fed9
[coreplex] rename Testing.scala -> RocketTestSuite.scala
2016-09-21 17:35:39 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
ed91e9a89b
Merge remote-tracking branch 'origin' into testharness-refactor
2016-09-20 13:03:21 -07:00
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
be9ddae77f
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
2016-09-15 13:04:01 -07:00
c6f252a913
Remove Option from success flag in coreplex; just use a sane default.
2016-09-15 12:19:22 -07:00
49863944c4
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
2016-09-14 21:36:27 -07:00
f5db83a72f
NTiles should not be a Knob
2016-09-14 21:16:54 -07:00
e404bea2ee
Merge branch 'master' into move-bootrom
2016-09-14 18:58:48 -07:00
97809b183f
refactor unittest framework
...
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
710f1ec020
Move BootROM from Coreplex to Periphery
2016-09-14 16:09:59 -07:00
565444c40e
Make UnitTestCoreplex cope with an external MMIO network
2016-09-14 12:19:21 -07:00
c3ddff809b
Move PRCI from Coreplex to always-on block, where it belongs
2016-09-14 11:01:05 -07:00
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
266a2f24bd
Disable Mul early out by default if XLen == 32
...
With a default unroll of 8, it doesn't help performance, but costs area.
2016-09-12 16:50:08 -07:00
f3cdeb08c6
pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 12:40:10 -07:00
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
