Wesley W. Terpstra
a12fea51e8
Plic: skip reserved interrupt in interrupt map printout
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
aabd17d935
rocketchip: must create bundles within Module scope
...
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs
Solution: pass a bundle constructor to the cake base class
Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.
Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d52615c39e
coreplex: one IntNode per tile
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e97844f71e
coreplex: make it possible to override the ConfigString
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
4de1822470
rocketchip: avoid using the nearly defunct GlobalAddrMap
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
688e1bffdf
rocketchip: pull rtcTick out of the coreplex
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
5bca13ebdb
rocketchip: use self-type constraints
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d51b0b5c02
rocketchip: use self-type
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
841a31479a
coreplex: fix TinyConfig
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
6505431eac
coreplex: use self-type constraints
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ac886026e6
rocketchip: reduce number of type parameters
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c
tilelink2 HintHandler: delay answers to help TL1 legacy clients
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
72a7948ad2
rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d2e9fa8ec6
Plic: remove path from ready to bits
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7
Debug: mark the debug device executable
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
401fd378b4
rocketchip: include devices from cbus in ConfigString
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
a73aa351ca
rocketchip: fix all clock crossings
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
89139a9492
Plic: split constants from variables used in config string
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
Megan Wachs
5090ff945b
DebugModule: Be more paranoid about addressing corner cases.
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
Megan Wachs
10d084b9f3
DebugModule: Use the power of RegisterRouter to simplify the DebugROM code.
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
3df797fcab
rocketchip: replace TL1 MMIO with an example of TL2 MMIO
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
082f338432
diplomacy Nodes: remove useless indirection
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
ec2d23b8b7
rocketchip: Bundle-slices need access to the outer LazyModule
...
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.
Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0dbda2f07d
rocketchip: remove obsolete pDevices used during TL1=>2 migration
2016-10-31 11:41:18 -07:00
Megan Wachs
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236
DebugModule: translate to TL2 with {32,64}-bit XLen width
2016-10-31 11:41:18 -07:00
Howard Mao
3e08d615f0
Merge pull request #427 from ucb-bar/put-after-release-bugfix
...
Fix issue with PutBlock and Release in BroadcastHub
2016-10-31 11:28:24 -07:00
Howard Mao
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
Howard Mao
cb81ea516c
add regression test for put-after-release bug
2016-10-28 18:26:34 -07:00
Howard Mao
fa8844d5c3
properly use rocket MT_ constants in regression tests
2016-10-28 18:26:34 -07:00
Andrew Waterman
f8bb67ab8f
Bind some Make vars early to avoid redundant evaluation
2016-10-28 11:56:13 -07:00
Andrew Waterman
f3c726033a
Make all Chisel invocations depend on FIRRTL_JAR
2016-10-28 11:56:05 -07:00
Andrew Waterman
2b65478f3a
bump chisel/firrtl
2016-10-28 00:36:53 -07:00
