Wesley W. Terpstra
aabd17d935
rocketchip: must create bundles within Module scope
...
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs
Solution: pass a bundle constructor to the cake base class
Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.
Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d52615c39e
coreplex: one IntNode per tile
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e97844f71e
coreplex: make it possible to override the ConfigString
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
688e1bffdf
rocketchip: pull rtcTick out of the coreplex
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d51b0b5c02
rocketchip: use self-type
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
841a31479a
coreplex: fix TinyConfig
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
6505431eac
coreplex: use self-type constraints
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ac886026e6
rocketchip: reduce number of type parameters
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
401fd378b4
rocketchip: include devices from cbus in ConfigString
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
a73aa351ca
rocketchip: fix all clock crossings
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
Wesley W. Terpstra
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
Megan Wachs
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
Andrew Waterman
53360f4c2c
Disable U-mode by default unless S-mode is present
2016-10-08 21:29:40 -07:00
Andrew Waterman
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
Andrew Waterman
968851f7e3
Default to configurable priorities
...
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Andrew Waterman
2bdf8c2be7
Merge branch 'master' into move-to-util
2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce
Default mtvec=0, not None
...
Setting it to None was a mistake. It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
2016-09-29 13:52:41 -07:00
Howard Mao
c45cc76cef
Get rid of remaining MemIO code
...
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
Howard Mao
7d6fb950b6
Give TileLink IDs more sensible names
...
* Outermost -> MCtoEdge
* MMIO_Outermost -> MMIOtoEdge
Then the corresponding parameters objects are
* L1toL2 -> innerParams
* L2toMC -> outerMemParams
* L2toMMIO -> outerMMIOParams
* MCtoEdge -> edgeMemParams
* MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01
move memory width adapter from coreplex to periphery
2016-09-27 12:48:01 -07:00
Howard Mao
201e247f73
Factor coreplex IO connection into separate trait ( #350 )
...
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.
The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
Howard Mao
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
Howard Mao
803739a95c
Make sure coreplex mmio's TLId is correct (thanks to zizztux)
2016-09-26 17:28:21 -07:00
Henry Cook
1e54820f8c
Merge remote-tracking branch 'origin/master' into unittest-config
2016-09-22 16:03:51 -07:00
Henry Cook
47c5d1a992
[WIP] Move RocketTestSuite generation into RocketchipGenerator
2016-09-22 14:31:45 -07:00
Yunsup Lee
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd
rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Henry Cook
fd5e00fed9
[coreplex] rename Testing.scala -> RocketTestSuite.scala
2016-09-21 17:35:39 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Henry Cook
ed91e9a89b
Merge remote-tracking branch 'origin' into testharness-refactor
2016-09-20 13:03:21 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Richard Xia
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
Andrew Waterman
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
Jack Koenig
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
Henry Cook
be9ddae77f
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913
Remove Option from success flag in coreplex; just use a sane default.
2016-09-15 12:19:22 -07:00