Andrew Waterman
a6e009d8de
[rocket] Fix frontend mask when fetchWidth == 1
2016-07-31 15:21:17 -07:00
Andrew Waterman
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
Andrew Waterman
d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
Andrew Waterman
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
Andrew Waterman
b8884e8143
Simplify frontend virtual address extension code
2016-07-14 12:05:09 -07:00
Andrew Waterman
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
Andrew Waterman
5aa8ef1855
Remove invalidation support from BTB
...
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
2016-07-02 14:27:29 -07:00
Howard Mao
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
Andrew Waterman
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
Andrew Waterman
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
Andrew Waterman
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
Yunsup Lee
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
Andrew Waterman
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
Andrew Waterman
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Andrew Waterman
dc662f28a0
Specify width on s1_pc to avoid width inference problem
2016-04-01 17:28:42 -07:00
Andrew Waterman
4480d1e817
Don't compile BTB when nEntries=0
2016-04-01 15:14:45 -07:00
Andrew Waterman
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
...
separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
Christopher Celio
f526d380fd
separate btb response mask from the frontend mask
...
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
120361226d
fix more Chisel3 deprecations
2016-01-14 14:46:31 -08:00
Howard Mao
13ce91e453
fix Chisel3 compat warnings in ICache and FPU
2016-01-12 12:43:48 -08:00
Howard Mao
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
Colin Schmidt
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
