128 lines
4.5 KiB
Scala
128 lines
4.5 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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import cde.{Parameters, Field}
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class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended)
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = Vec(Bits(width = coreInstBits), fetchWidth)
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val mask = Bits(width = fetchWidth)
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val xcpt_if = Bool()
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}
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class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val invalidate = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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}
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class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
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val io = new Bundle {
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val cpu = new FrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = new ClientUncachedTileLinkIO
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}
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val btb = Module(new BTB)
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val icache = Module(new ICache)
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val tlb = Module(new TLB)
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val s1_pc_ = Reg(UInt())
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val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(btb.io.resp.bits)
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val s2_xcpt_if = Reg(init=Bool(false))
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val icbuf = Module(new Queue(new ICacheResp, 1, pipe=true))
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val msb = vaddrBits-1
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val lsb = log2Up(fetchWidth*coreInstBytes)
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val ntpc_0 = s1_pc + UInt(coreInstBytes*fetchWidth)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
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val icmiss = s2_valid && !icbuf.io.deq.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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s1_same_block := s0_same_block && !tlb.io.resp.miss
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s1_pc_ := npc
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s2_valid := !icmiss
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when (!icmiss) {
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s2_pc := s1_pc
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s2_btb_resp_valid := btb.io.resp.valid
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when (btb.io.resp.valid) { s2_btb_resp_bits := btb.io.resp.bits }
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s2_xcpt_if := tlb.io.resp.xcpt_if
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}
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}
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when (io.cpu.req.valid) {
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s1_same_block := Bool(false)
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s1_pc_ := io.cpu.req.bits.pc
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s2_valid := Bool(false)
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}
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btb.io.req.valid := !stall && !icmiss
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
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tlb.io.req.bits.asid := UInt(0)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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tlb.io.req.bits.store := Bool(false)
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io.mem <> icache.io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := io.cpu.npc
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid ||
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tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
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icmiss || io.ptw.invalidate
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icbuf.io.deq.valid)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icbuf.io.enq <> icache.io.resp
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icbuf.io.deq.ready := !stall && !s1_same_block
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require(fetchWidth * coreInstBytes <= rowBytes)
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val fetch_data =
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if (fetchWidth * coreInstBytes == rowBytes) icbuf.io.deq.bits.datablock
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else icbuf.io.deq.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(fetchWidth*coreInstBytes)) << log2Up(fetchWidth*coreInstBits))
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for (i <- 0 until fetchWidth) {
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io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
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}
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val all_ones = UInt((1 << (fetchWidth+1))-1)
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val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
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io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.btb_resp.valid := s2_btb_resp_valid
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io.cpu.btb_resp.bits := s2_btb_resp_bits
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}
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