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Commit Graph

66 Commits

Author SHA1 Message Date
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
4f388add67 More accurate conditional include of generated .d make fragment (#222) 2016-08-25 14:42:04 -07:00
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
07f0e6be94 Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
c2344ee2bc Added generated-src-debug to make clean target 2015-09-11 19:07:33 -07:00
8f71c4da2d Reintroduced multiple emulator backend directories
Fixes a "make -j" concurrency bug due to deleting files that another
  parallel rule depends on.
2015-09-10 17:14:23 -07:00
ee531dc97e Add missing changes to emulator/Makefile 2015-07-29 18:15:21 -07:00
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
854fd64fba Added optional Makefile includes for private chip repos 2015-07-06 17:15:27 -07:00
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
879a4a0bcd Update Makefile
Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
484648d9c7 Changed CONFIG from a recursively expanded variable to a conditionally
assigned variable, allowing users to define CONFIG external to Makefile
2014-09-17 11:12:02 -07:00
275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
0ca24a5d91 fix debug flags 2014-08-12 10:35:39 -07:00
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
fc52840ce2 move timeout in Makefile to a variable 2014-01-31 16:52:59 -08:00
e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
6aa500fc16 dont make assumptions about default project name when invoking sbt 2013-08-20 12:56:01 -07:00
b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
4ae0c68303 require -std=c++11, as -std=c++0x doesn't cut it 2013-06-14 00:28:42 -07:00
896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
85fbb650c9 makefile support for new multithreading tests 2013-06-13 15:34:54 -07:00
a86ad08c1e commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
c6b56c5f25 bump rocket for coherence bug fix 2013-04-04 15:52:20 -07:00
def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00