Andrew Waterman
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a0378c5d2f
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remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
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2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
6d8fc74378
|
fix DTLB permissions bug
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2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
54fa6f660d
|
new supervisor mode
|
2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
|
7493d55d3f
|
add pf fault handling
|
2012-03-18 15:06:39 -07:00 |
|
Yunsup Lee
|
8678b3d70c
|
clean up ioDecoupled/ioPipe interface
|
2012-03-01 20:48:46 -08:00 |
|
Andrew Waterman
|
c38065d0e8
|
clean up priority encoders
|
2012-02-29 16:13:14 -08:00 |
|
Andrew Waterman
|
1d41a41afa
|
remove extraneous constants
|
2012-02-27 17:49:48 -08:00 |
|
Yunsup Lee
|
bfd0ae125e
|
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
|
2012-02-26 23:46:51 -08:00 |
|
Andrew Waterman
|
2d04664a98
|
simplify cpu-cache interface
|
2012-02-26 18:26:29 -08:00 |
|
Daiwei Li
|
69260756bd
|
change ppn and vpn in dtlb from ufix to bits
|
2012-02-26 02:54:31 -08:00 |
|
Daiwei Li
|
569698b824
|
dtlb now arbitrates between cpu, vec, and vec pf
|
2012-02-25 22:05:30 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Andrew Waterman
|
f1c355e3cd
|
check pc/effective address sign extension
|
2012-01-24 00:15:17 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
0369b05deb
|
move replays to writeback stage
|
2012-01-17 21:12:31 -08:00 |
|
Andrew Waterman
|
92dda102b6
|
slight control logic cleanup
|
2012-01-11 16:56:40 -08:00 |
|
Andrew Waterman
|
2f8fcebea0
|
remove datapath register resets resets
|
2012-01-01 16:09:40 -08:00 |
|
Andrew Waterman
|
a8d0cd95e6
|
hellacache now works
|
2011-12-17 03:26:11 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Andrew Waterman
|
a87ad06780
|
Automatically infer rocketCAM address width
|
2011-12-06 02:05:40 -08:00 |
|
Rimas Avizienis
|
5a322ff00c
|
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
|
2011-11-17 11:17:37 -08:00 |
|
Rimas Avizienis
|
ae98956e6b
|
more amo fixes, added more options to testharness to control debug messages
|
2011-11-15 02:43:51 -08:00 |
|
Rimas Avizienis
|
9d3471a569
|
more cache fixes, more test harness debug output
|
2011-11-13 23:32:18 -08:00 |
|
Rimas Avizienis
|
fbd44ea936
|
added checks for addresses > physical memory size, increased memsize to 64M
|
2011-11-12 23:39:43 -08:00 |
|
Rimas Avizienis
|
91c252ad08
|
fixing output enable signals for data/tag SRAMs
|
2011-11-12 15:47:47 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
44926866b7
|
updated itlb
|
2011-11-11 18:48:34 -08:00 |
|
Rimas Avizienis
|
a1ce908541
|
dcache/dtlb overhaul
|
2011-11-11 18:18:47 -08:00 |
|
Rimas Avizienis
|
e4fa94aa27
|
checkpoint
|
2011-11-10 17:41:22 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
|
moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|
Rimas Avizienis
|
62407b4668
|
more tlb/ptw fixes
|
2011-11-10 00:23:29 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|