01b0f6a52b
ahb: new diplomacy-based AHB bus definition
2016-12-08 18:00:39 -08:00
54cc071a64
Fix Fragmenter to ensure logical operations must be sent out atomically.
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Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
1bd8a2e239
Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections
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Parameterize diplomatic connections
2016-12-07 15:03:53 -08:00
c2eedbfe23
tilelink2 Monitor: use Parameters instead of global variables
2016-12-07 12:24:03 -08:00
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
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This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
915697cb09
Fix FEQ flag generation ( #479 )
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FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
fbfa15efea
TLBroadcast: support non-FIFO devices ( #482 )
2016-12-05 22:10:37 -08:00
3c9718ec8f
clint: undefined registers must be zero ( #480 )
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This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
2016-12-05 17:11:53 -08:00
f3d0692619
Make a directory for the config package ( #464 )
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* [config] make dir structure mirror packages
* [config] expunge max_int
2016-12-05 10:42:16 -08:00
d0a0c887dc
[tracegen] decrease default address bag size ( #462 )
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while increasing the default number of requests.
2016-12-04 22:46:55 -08:00
36fe024671
CacheName no longer needed in RoCCInterface
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With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
9fb7934a37
WIP PR to figure out why travis is failing ( #471 )
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Make travis use a docker image with pre-built toolchain and verilator
2016-12-04 13:10:13 -08:00
9ac78a0d37
Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
2016-12-02 14:21:36 -08:00
e8d3b647f2
Removed val from case class for Parameters
2016-12-02 14:21:15 -08:00
053f81d7c6
minor Changes needed to support formal tests
2016-12-02 14:21:15 -08:00
aa39b3d09d
Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
2016-12-01 18:37:13 -08:00
be23189f77
Removed val from case class for Parameters
2016-12-01 18:36:18 -08:00
6d402ff1af
minor Changes needed to support formal tests
2016-12-01 18:36:18 -08:00
60889df576
Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
2016-12-01 15:17:30 -08:00
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
a49b6d6569
Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
2016-12-01 15:01:52 -08:00
5e9496fd14
minor Changes needed to support formal tests
2016-12-01 14:56:16 -08:00
75512e9aa0
minor Changes needed to support formal tests
2016-12-01 14:55:25 -08:00
4234cff074
Merge pull request #444 from ucb-bar/bump-submodules
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rocketchip: bump all submodules (and remove cde)
2016-11-29 00:13:00 -08:00
131659cc2a
Merge branch 'master' into bump-submodules
2016-11-28 16:20:42 -08:00
d07e30ba97
Update README.md
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fixed torture link
2016-11-28 16:19:09 -08:00
a8ee7e0678
Update README
2016-11-28 16:10:50 -08:00
18d100c2b5
Merge pull request #461 from ucb-bar/sifive-copyright
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Sifive copyright
2016-11-28 15:25:33 -08:00
86065e5fb8
Merge remote-tracking branch 'origin/master' into bump-submodules
2016-11-28 13:49:59 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
d4708694ea
scripts/authors: Matthew Naylor's submissions were under Berkeley terms
2016-11-27 22:15:43 -08:00
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
8510d9e697
scripts: two scripts to determine copyright holder of files
2016-11-27 22:15:38 -08:00
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
97a853a995
Merge pull request #459 from ucb-bar/bump-chisel-for-firrtl-jar-gitignore
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Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
2016-11-26 13:55:53 -08:00
4e3682f889
Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
2016-11-26 12:24:10 -08:00
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
9433da8458
Merge pull request #457 from ucb-bar/jtag-depth-1
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Jtag depth 1
2016-11-25 18:41:39 -08:00
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
f19d504c88
Use % in makefrag-verilog to prevent double firrtl execution ( #452 )
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* Use % in makefrag-verilog to prevent double firrtl execution
2016-11-25 01:50:01 -08:00
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
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This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
549e006988
Merge pull request #451 from ucb-bar/more-configs
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More configs
2016-11-24 09:44:52 -08:00
6aeadc4551
regression: disable ComparatorL2Config for now
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This tests atomics against the L2. However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
2016-11-23 20:53:36 -08:00
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
