Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
|
4121fb178c
|
clean up mul/div interface; use VU mul if HAVE_VEC
|
2012-02-24 19:22:35 -08:00 |
|
Daiwei Li
|
477f3cde02
|
added prefetch queues for vu
|
2012-02-24 00:44:13 -08:00 |
|
Andrew Waterman
|
5332bab6f1
|
expose FMA ports outside of FPU (for the VU)
|
2012-02-23 17:39:34 -08:00 |
|
Andrew Waterman
|
7c929afe2b
|
HTIF now controls CPU reset
|
2012-02-22 19:30:03 -08:00 |
|
Daiwei Li
|
22f8dd0994
|
Hook up resp_type to vector unit
|
2012-02-21 18:20:32 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Yunsup Lee
|
82cd3625c2
|
add in vackq interface
|
2012-02-15 17:53:24 -08:00 |
|
Yunsup Lee
|
32bdf5098a
|
refactor vector control logic & datapath in the rocket core
|
2012-02-15 13:30:22 -08:00 |
|
Yunsup Lee
|
7c11c1406c
|
vector-vector add working!
|
2012-02-15 02:28:07 -08:00 |
|
Yunsup Lee
|
6bdf9dc513
|
hwacha integration: now it compiles correctly!
|
2012-02-14 23:34:57 -08:00 |
|
Andrew Waterman
|
15dc2d8c40
|
add fp writeback arbitration logic
|
2012-02-14 00:32:25 -08:00 |
|
Andrew Waterman
|
069037ff3a
|
add FP recoding
|
2012-02-12 23:31:50 -08:00 |
|
Andrew Waterman
|
08b6517a23
|
add FP ops mftx, mxtf, mtfsr, mffsr
|
2012-02-12 20:12:53 -08:00 |
|
Andrew Waterman
|
9bb1558a34
|
WIP on FPU
|
2012-02-12 04:36:01 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
|
8b6b0f5367
|
add external memory request interface for vec unit
|
2012-02-08 22:30:45 -08:00 |
|
Yunsup Lee
|
9285a52f25
|
initial vu integration
|
2012-02-08 21:43:45 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
|
f1c355e3cd
|
check pc/effective address sign extension
|
2012-01-24 00:15:17 -08:00 |
|
Henry Cook
|
8766438bb9
|
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
|
2012-01-23 17:09:23 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
1a7bfd4350
|
remove icache req_rdy signal
|
2012-01-11 18:27:11 -08:00 |
|
Andrew Waterman
|
bcb55e581a
|
remove host.start signal, use reset instead
|
2012-01-11 17:49:32 -08:00 |
|
Andrew Waterman
|
92dda102b6
|
slight control logic cleanup
|
2012-01-11 16:56:40 -08:00 |
|
Andrew Waterman
|
142dfc6e07
|
made tohost/fromhost 64 bits wide
|
2012-01-03 15:09:08 -08:00 |
|
Andrew Waterman
|
3045b33460
|
remove second RF write port
load miss writebacks are treated like mul/div now.
|
2012-01-02 02:51:30 -08:00 |
|
Andrew Waterman
|
ffe23a1ee8
|
fix WAW hazard handling
|
2012-01-02 00:25:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Rimas Avizienis
|
da2fdf4f85
|
fixed console i/o
|
2011-11-30 22:51:59 -08:00 |
|
Rimas Avizienis
|
11f0e3daf4
|
more cleanup
|
2011-11-18 00:17:30 -08:00 |
|
Rimas Avizienis
|
c42d8149b7
|
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
|
2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
|
48cec01710
|
updated riscv-bmarks and riscv-tests to build with new toolchain
|
2011-11-15 00:11:22 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
5f4b15b809
|
added ld/st misaligned exceptions
|
2011-11-13 00:03:17 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
73416f224b
|
more tlb/ptw debugging
|
2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
|
44926866b7
|
updated itlb
|
2011-11-11 18:48:34 -08:00 |
|
Rimas Avizienis
|
a1ce908541
|
dcache/dtlb overhaul
|
2011-11-11 18:18:47 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
|
moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|
Rimas Avizienis
|
62407b4668
|
more tlb/ptw fixes
|
2011-11-10 00:23:29 -08:00 |
|
Rimas Avizienis
|
6664af3bc0
|
cleanup before adding dtlb
|
2011-11-09 23:27:29 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
4459935554
|
dcache fixes - all tests and ubmarks pass, hello world still broken
|
2011-11-04 15:40:41 -07:00 |
|
Rimas Avizienis
|
7a528d6255
|
fixes for div/mul hazard checking + cleanup
|
2011-11-01 23:14:34 -07:00 |
|