128 lines
4.5 KiB
Scala
128 lines
4.5 KiB
Scala
package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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class ioDebug(view: List[String] = null) extends Bundle(view)
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{
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val error_mode = Bool('output);
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val log_control = Bool('output);
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val id_valid = Bool('output);
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val ex_valid = Bool('output);
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val mem_valid = Bool('output);
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val wb_valid = Bool('output);
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}
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class ioHost(view: List[String] = null) extends Bundle(view)
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{
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val start = Bool('input);
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val from_wen = Bool('input);
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val from = Bits(32, 'input);
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val to = Bits(32, 'output);
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}
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class ioConsole(view: List[String] = null) extends Bundle(view)
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{
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val rdy = Bool('input);
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val valid = Bool('output);
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val bits = Bits(8, 'output);
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}
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class ioRocket extends Bundle()
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{
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val debug = new ioDebug();
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val console = new ioConsole();
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val host = new ioHost();
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val imem = new ioImem().flip();
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val dmem = new ioDmem().flip();
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}
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class rocketProc extends Component
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{
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val io = new ioRocket();
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val ctrl = new rocketCtrl();
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val dpath = new rocketDpath();
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val dtlb = new rocketDTLB(DTLB_ENTRIES);
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val itlb = new rocketITLB(ITLB_ENTRIES);
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val ptw = new rocketPTW();
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val arb = new rocketDmemArbiter();
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ctrl.io.dpath <> dpath.io.ctrl;
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ctrl.io.host.start ^^ io.host.start;
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// ctrl.io.dmem ^^ io.dmem;
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// ctrl.io.imem ^^ io.imem;
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// dpath.io.dmem ^^ io.dmem;
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// dpath.io.imem.req_addr ^^ io.imem.req_addr;
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dpath.io.imem.resp_data ^^ io.imem.resp_data;
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dpath.io.host ^^ io.host;
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dpath.io.debug ^^ io.debug;
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// FIXME: make this less verbose
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// connect ITLB to I$, ctrl, dpath
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itlb.io.cpu.invalidate := Bool(false); // FIXME
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itlb.io.cpu.status := dpath.io.ctrl.status;
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itlb.io.cpu.req_val := ctrl.io.imem.req_val;
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itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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itlb.io.cpu.req_addr := dpath.io.imem.req_addr;
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io.imem.req_val := itlb.io.cpu.resp_val;
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io.imem.req_addr := itlb.io.cpu.resp_addr;
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ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
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ctrl.io.imem.resp_val := io.imem.resp_val;
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ctrl.io.itlb_xcpt := itlb.io.cpu.exception;
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// connect DTLB to D$ arbiter, ctrl+dpath
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dtlb.io.cpu.invalidate := Bool(false); // FIXME
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dtlb.io.cpu.status := dpath.io.ctrl.status;
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dtlb.io.cpu.req_val := ctrl.io.dmem.req_val;
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dtlb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
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dtlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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dtlb.io.cpu.req_addr := dpath.io.dmem.req_addr;
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ctrl.io.dtlb_xcpt := dtlb.io.cpu.exception;
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.dtlb <> dtlb.io.ptw;
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.ptw <> ptw.io.dmem;
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arb.io.mem ^^ io.dmem
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// FIXME: make this less verbose
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// connect arbiter to ctrl+dpath
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arb.io.cpu.req_val := dtlb.io.cpu.resp_val;
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arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
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arb.io.cpu.req_type := ctrl.io.dmem.req_type;
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arb.io.cpu.req_addr := dtlb.io.cpu.resp_addr;
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arb.io.cpu.req_data := dpath.io.dmem.req_data;
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arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
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ctrl.io.dmem.req_rdy := dtlb.io.cpu.req_rdy && arb.io.cpu.req_rdy;
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ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
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dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
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dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
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// arb.io.cpu.req_val := ctrl.io.dmem.req_val;
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// arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
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// arb.io.cpu.req_type := ctrl.io.dmem.req_type;
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// arb.io.cpu.req_addr := dpath.io.dmem.req_addr;
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// arb.io.cpu.req_data := dpath.io.dmem.req_data;
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// arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
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// ctrl.io.dmem.req_rdy := arb.io.cpu.req_rdy;
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// ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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// ctrl.io.dmem.resp_val := arb.io.cpu.resp_val;
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// dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
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// dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
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// dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
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// FIXME: console disconnected
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// io.console.bits := dpath.io.dpath.rs1(7,0);
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io.console.bits := Bits(0,8);
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io.console.valid := ctrl.io.console.valid;
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ctrl.io.console.rdy := io.console.rdy;
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}
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}
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