Wesley W. Terpstra
36f4584bb1
axi4: Test AXI4-Lite in regression
2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845
axi4: SRAM support 0 userBits
2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86
axi4: Deinterleaver must gather R also for single ID
...
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2
axi4: IdIndexer; a single ID does NOT imply no response interleaving
...
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411
axi4: IdIndexer now handles 0-width IDs
2017-05-08 00:17:02 -07:00
Scott Johnson
1cc665717d
Wes fix for AXI2TL timeout when writes backed up
2017-05-04 00:54:21 -07:00
Henry Cook
1f1240baf1
fuzzer: allow fuzzing range to be overridden
2017-05-03 15:29:14 -07:00
Wesley W. Terpstra
fe280187a1
axi4: Fragmenter cuts all input channel readys
...
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d
axi4: ToTL correct error handling
...
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d
axi4: switch arbiter to round robin
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43
diplomacy: optimize IdRange overlap detection
2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9
Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd
axi4: make maxFlight a per-master parameter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644
axi4: massage test cases into shape again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196
axi4: get unit tests legal again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156
axi4: Deinterleaver ensures R channel ID does not change till last
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd
rocketchip: fix uses of AXI4 Fragmenter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea
axi4: simplify Fragmenter by using user bits
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
a580b17ece
axi4: IdIndexer => reduce number of needed ids
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96
axi4: an adapter to remove user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1
axi4: RegisterRouter; concurrent response illegal in AXI
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f
axi4: RegisterRouter supports user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442
axi4: support user bits in SRAM
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4
AXI4: add an optional user bundle field
2017-05-01 22:53:01 -07:00
Henry Cook
ca435c2f40
uncore: more verbose requires
2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
Henry Cook
6958f05a85
Merge remote-tracking branch 'origin/master' into periphery-adjustments
2017-02-27 19:40:55 -08:00
Andrew Waterman
dfa61bc487
Standardize Data.holdUnless and SeqMem.readAndHold
...
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
735e4f8ed6
diplomacy: use HeterogeneousBag instead of Vec
...
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
2017-02-22 17:05:22 -08:00
Wesley W. Terpstra
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
f7f52cc722
diplomacy: restore Monitor functionality
2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
64e1de751d
axi4: add a minLatency parameter
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
9dc7f180b6
diplomacy: support zero-port Nodes
2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
e7b35b4bb6
diplomacy: support multiple ports behind a BlindNode
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Wesley W. Terpstra
d067e87a7d
tilelink2 Parameters: sinkId is per port, not per manager
2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
015c3b862a
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00