8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
36720d915a
Update README.md ( #161 )
...
Correct typo in heading
2016-07-11 00:34:13 -07:00
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
2a146155fc
Update to new priv-1.9 PTE format
2016-07-06 10:15:59 -07:00
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
af51b6f363
bump groundtest and uncore
2016-07-01 18:13:46 -07:00
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
800e62412a
use the fast version of asm/bmark-tests
2016-06-24 15:36:10 -07:00
d6ba0437ff
merge different configs into regression suites to reduce travis build times
2016-06-24 13:02:29 -07:00
87a4858aa6
Exit from testbench, not C code
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Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
4cd709c516
fix Comparator in groundtest
2016-06-23 15:47:24 -07:00
568bfa6c50
Purge legacy HTIF things
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The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
255ef05e21
bump rocket
2016-06-22 17:59:05 -07:00
338f959620
get rid of commented out code
2016-06-22 17:36:53 -07:00
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
5edb448a1f
get rid of slow DualCoreConfig in Travis for now
2016-06-22 16:09:14 -07:00
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
9b9ddd0d54
get rid of leftover backup memory code
2016-06-22 16:06:41 -07:00
e3d3b2264a
fix MuxCase and MuxLookup
2016-06-21 14:03:10 -07:00
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
4a8e6c773a
Fix +verbose flag for verilator
2016-06-17 21:09:08 -07:00
25ade44fe3
Don't build the Verilator man pages ( #141 )
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These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
2016-06-16 10:13:21 -07:00
ba35712f08
Merge pull request #140 from ucb-bar/verilator
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Default to Chisel 3
2016-06-15 16:25:07 -07:00
68ba33369b
Default to Chisel 3
...
Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
2016-06-15 14:01:43 -07:00
e617bb8aa8
Start testing Chisel 3 in Travis
...
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis. This disables Chisel 2 Travis tests because they're
too slow.
2016-06-15 14:01:22 -07:00
f6432395cb
Allow the regressions to run more than once
2016-06-14 21:21:44 -07:00
1525b4717e
Install Verilator when building the emulator
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We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
2016-06-14 21:21:43 -07:00
