Megan Wachs
8856953905
DescribedReg: move to regmapper
2018-03-05 16:12:14 -08:00
Megan Wachs
e3be5db3e6
BUE: more verbose register descriptions
2018-03-05 12:02:42 -08:00
Megan Wachs
878a357a0d
RegFieldDesc: Add utilities for generating and describing registers at the same time.
2018-03-05 12:02:42 -08:00
Andrew Waterman
644ba6dafa
Add BusErrorUnit RegFieldDesc
2018-03-02 17:25:13 -08:00
Jack Koenig
8c6e745653
Bump chisel and firrtl ( #1232 )
...
* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
2018-03-01 15:19:12 -08:00
Henry Cook
20a8876856
Merge pull request #1190 from freechipsproject/bus-api
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BusWrapper API Update
2018-03-01 01:13:50 -08:00
Megan Wachs
cdd2a9227f
Merge pull request #1256 from freechipsproject/json_emit_enums
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RegFieldDesc: Emit enumerations into JSON if they exist
2018-02-28 11:32:14 -08:00
Megan Wachs
d13dc8ac2a
RegFieldDesc: Emit enumerations if they exist
2018-02-28 09:42:25 -08:00
Andrew Waterman
a48dd575b2
Merge pull request #1254 from freechipsproject/amo-aqrl
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Fix mapping of acquire/release AMOs to fence operations
2018-02-27 19:49:40 -06:00
bipult
47d63d6baa
Merge pull request #1251 from freechipsproject/rocket_covers
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Added functional covers
2018-02-25 09:01:33 -08:00
Andrew Waterman
eb6e192ec0
Fix mapping of acquire/release AMOs to fence operations
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AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO. These had been swapped. This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).
Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations. For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
2018-02-23 16:39:47 -08:00
Henry Cook
30c0635bb3
subsystem: add some inter-wrapper buffer params
2018-02-23 15:31:18 -08:00
Wesley W. Terpstra
95294bbdcb
PatternPusher: put data at correct address when misaligned ( #1249 )
2018-02-23 15:20:56 -08:00
Henry Cook
ad823ef43c
subsystem: pbus crossing type
2018-02-23 13:52:18 -08:00
Henry Cook
5725e17969
subsystem: even more general coupler methods
2018-02-23 13:52:12 -08:00
Jacob Chang
87eed645d8
Fix JTAG cover description ( #1248 )
2018-02-23 12:13:31 -08:00
Henry Cook
5b1d72c776
subsystem: expose HasTiles Parameters
2018-02-22 23:46:08 -08:00
Henry Cook
099bbec666
subsystem: more buswrapper coupling methods
2018-02-22 23:45:21 -08:00
Bipul Talukdar
2e548c9ad2
Added functional covers
2018-02-22 23:20:12 -08:00
Andrew Waterman
aad75f2285
Implement misa.C proposal
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This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
Andrew Waterman
c1ee31d133
Fix debug trigger point for stores
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In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after. Previously, we reported the exception
on the store's PC, but the store occurred anyway. This probably
hasn't been problematic in practice because most stores are
idempotent.
2018-02-22 14:56:57 -08:00
Henry Cook
78883d13e8
subsystem: add TLIdentity.gen and make wrappers more flexible
2018-02-21 18:22:06 -08:00
Henry Cook
eaa908d44f
subsystem: more buswrapper methods
2018-02-21 14:52:59 -08:00
Henry Cook
e237f72539
subsystem: XSubsystemModule => XSubsystemModuleImp
2018-02-21 14:52:59 -08:00
Henry Cook
1af02f754e
groundtest: fix filename
2018-02-21 14:52:59 -08:00
Henry Cook
030c6f0206
subsystem: bus wrappers now in BaseSubsystem
2018-02-21 14:52:59 -08:00
Henry Cook
b617e26c13
util: augment String and use to name couplers
2018-02-21 14:43:47 -08:00
Henry Cook
a6d3965491
tilelink: bus wrapper scopes called 'couplers'
2018-02-21 14:43:47 -08:00
Henry Cook
57edd7facf
subsystem: streamline toTile and fromTile attachment
2018-02-21 14:43:47 -08:00
Wesley W. Terpstra
ef3addee7b
diplomacy: put full module + instance path into graphml Description
2018-02-21 14:43:47 -08:00
Henry Cook
62aee56807
diplomacy: base instance names on ValName and module names on className
2018-02-21 14:43:47 -08:00
Henry Cook
3f436a7612
subsystem: new bus attachment api
2018-02-21 14:43:47 -08:00
Henry Cook
8462ea3d5b
coreplex => subsystem
2018-02-21 14:42:24 -08:00
Andrew Waterman
8998a97ea1
Preserve WithRV32 behavior: FLEN = 32
2018-02-20 18:28:47 -08:00
Andrew Waterman
1dc1e2c099
support testing RV32D configs
2018-02-20 16:16:39 -08:00
Andrew Waterman
d4fb7ad6a2
DefaultRV32Config should provide fdiv/fsqrt
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This is a holdover from before we had built the functional unit.
2018-02-20 16:16:39 -08:00
Andrew Waterman
b487448961
Add FPUParams.fLen option, decoupled from xLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
5e35015651
Minor Rocket fixes to support fLen != xLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
bd29184e11
debug: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
62f9b84439
plic: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
52e22a1dd8
clint: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
Andrew Waterman
1bac2cbdf8
Give Rocket priority over DTIM TL port
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The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline. Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads. Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
Megan Wachs
5affd3bec2
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 10:24:12 -08:00
Megan Wachs
cf7cd03d64
Merge pull request #1239 from freechipsproject/reduce_debug_flags
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Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
Megan Wachs
d72abb7a12
Debug: revert change to how flags are named
2018-02-15 21:49:32 -08:00
Wesley W. Terpstra
dcfbdabe60
CacheCork: better document edge conditions
2018-02-15 19:14:30 -08:00
Wesley W. Terpstra
ecd069dca4
tilelink: allow FIFO caches
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Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
Wesley W. Terpstra
acecc407a5
HellaCache: we do NOT really support probe below the block size!
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If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
Megan Wachs
c34b940d9a
ElaborationArtefacts: revert unintentional change
2018-02-15 14:23:54 -08:00
Megan Wachs
e0c3b22d61
RegFieldDesc: same string used to insert/compare
2018-02-15 14:23:27 -08:00
