270011b768
[unittest] more Config cleanup
2016-09-21 17:30:14 -07:00
2522bdd7b8
Merge pull request #321 from ucb-bar/add-multiclock-coreplex
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add multiclock support to Coreplex
2016-09-21 17:23:34 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
8e63f4a1a5
Remove ClockToSignal and vice-versa
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Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
2ab61f1a71
Chisel implicit clock is now named clock, not clk
2016-09-21 16:16:47 -07:00
335e866176
[unittest] Parallelize UnitTestSuite ( #319 )
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* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.
* [util] Timer spacing cleanup
* [unittest] Remove Config reference to UnitTestTimeout
2016-09-21 13:05:22 -07:00
12d0c00822
Fix mtime RegField handling
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RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking. Avoid RegField.bytes by splitting mtime into
a Seq of words.
2016-09-20 15:00:52 -07:00
6f6480ad9f
Merge pull request #303 from ucb-bar/testharness-refactor
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TestHarness refactoring
2016-09-20 14:45:05 -07:00
40f6f31611
[unittest] further refactor unittest framework
2016-09-20 14:14:30 -07:00
ed91e9a89b
Merge remote-tracking branch 'origin' into testharness-refactor
2016-09-20 13:03:21 -07:00
b97a0947a9
[rocketchip] enable piecewise Generator output
2016-09-20 12:57:56 -07:00
74fc7c5803
Merge pull request #315 from ucb-bar/fix-addrmap-error-msg
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correctly print out the addrmap overlapping error message
2016-09-19 19:39:56 -07:00
1a09e46f69
Merge branch 'master' into fix-addrmap-error-msg
2016-09-19 18:08:58 -07:00
15e7041ccb
Merge pull request #316 from ucb-bar/dynamic-reset-vector
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Allow reset vector to be set dynamically
2016-09-19 18:00:25 -07:00
3b38736a8e
Make BaseTopModule and BaseTopModule abstract
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They aren't meant to be directly instantiated.
2016-09-19 17:18:35 -07:00
d0572d6aab
Allow reset vector to be set dynamically
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A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
2961d92244
[testharness] vsim makefrag cleanup
2016-09-19 15:14:45 -07:00
1b26d78114
correctly print out the addrmap overlapping error message
2016-09-19 13:34:58 -07:00
df442ed82c
[rocketchip] avoid pending merge conflict]
2016-09-19 13:24:01 -07:00
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
7b8aa6c839
[rocketchip] split out Base and Example tops
2016-09-19 11:00:13 -07:00
7ff7076dab
Merge pull request #310 from ucb-bar/rxia-testharness-refactor
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Resolve merge conflicts in testharness-refactor
2016-09-19 10:22:49 -07:00
f0debb89e4
Merge pull request #314 from ucb-bar/widecounter-reset
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Allow WideCounter to not be reset
2016-09-18 22:37:40 -07:00
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
aa956c0108
Merge pull request #312 from ucb-bar/tl2-cheap-address-decode
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Tl2 cheap address decode
2016-09-17 17:37:03 -07:00
9817a00ed9
tilelink2: Fuzzer should check address validity before injection
2016-09-17 17:07:21 -07:00
b11839f5a1
tilelink2: differentiate fast/safe address lookup cases
2016-09-17 17:04:18 -07:00
b4baae4214
tilelink2: minimize Xbar decode logic
2016-09-17 16:14:25 -07:00
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
fa0f119f3c
tilelink2: consider the implications of negative address mask
2016-09-17 16:14:22 -07:00
e437508548
tilelink2: track interrupt connectivity like in TL2
2016-09-17 14:43:48 -07:00
fd3ac4653c
Merge pull request #311 from ucb-bar/rom-executable
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Rom executable
2016-09-17 01:28:52 -07:00
01c1886b9d
Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
6c3269a1d8
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
e749558190
ROM: optionally (default: true) executable
2016-09-17 00:19:09 -07:00
c70045b8b3
Utils: express cacheability from TL2 to TL1
2016-09-17 00:16:40 -07:00
e3d2bd3323
Top: print memory region properties, RWX [C]
2016-09-17 00:16:00 -07:00
75c73fce37
Merge pull request #309 from ucb-bar/tl2-addrmap
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Tl2 addrmap
2016-09-16 19:09:22 -07:00
5c858685aa
Utils: support managers with multiple addresses
2016-09-16 18:03:49 -07:00
3fdf40c088
Change implicit argument to explicit.
2016-09-16 17:47:31 -07:00
a9382b3116
Periphery: test bench looks for "testram"
2016-09-16 17:47:20 -07:00
b5ce6150c7
Periphery: dynamically create address map + config string for TL2
2016-09-16 17:28:47 -07:00
8876d83640
Prci: preserve Andrew's preferred clint name
2016-09-16 17:28:47 -07:00
a357c1d42e
tilelink2: create DTS for devices automagically
2016-09-16 17:28:47 -07:00
2587234838
tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
2016-09-16 17:28:47 -07:00
915a929af1
tilelink2: Nodes can now mix context into parameters
2016-09-16 17:28:47 -07:00
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
503ce14c98
Merge pull request #307 from ucb-bar/address-shrink
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RR: undefined regs return zeros
2016-09-16 16:55:35 -07:00
dae0918c85
tilelink2 RegisterRouter: support undefZero
2016-09-16 16:09:00 -07:00
