Henry Cook
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78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
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Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
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Henry Cook
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a41d55b643
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Final parameter refactor.
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2014-08-23 01:26:03 -07:00 |
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Henry Cook
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2741bbf2b9
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Point rocket/ to rocket-staging repo
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2014-08-19 13:53:24 -07:00 |
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Henry Cook
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1563c1bb36
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Fixed cache params. Asm and bmark tests pass.
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2014-08-12 15:00:54 -07:00 |
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Henry Cook
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910c886837
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bump chisel
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2014-08-12 14:53:19 -07:00 |
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Henry Cook
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74796868e7
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chisel bump
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2014-08-12 10:58:09 -07:00 |
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Henry Cook
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0ca24a5d91
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fix debug flags
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2014-08-12 10:35:39 -07:00 |
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Henry Cook
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7f07771600
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:37:10 -07:00 |
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Henry Cook
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1983260e6f
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-10 23:08:21 -07:00 |
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Henry Cook
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63bd0b9d2a
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Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
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2014-08-08 12:27:47 -07:00 |
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Adam Izraelevitz
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08d81d0892
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First cut at using new chisel parameters for toplevel parameters and fpu
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2014-08-01 18:09:37 -07:00 |
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Adam Izraelevitz
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fcd68364ff
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Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
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2014-08-01 18:07:22 -07:00 |
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Henry Cook
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434da22283
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
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2014-05-28 17:16:49 -07:00 |
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Henry Cook
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b0ccb88982
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make outer cache type choice a top-level const
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2014-05-28 14:46:07 -07:00 |
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Stephen Twigg
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d2a3b1dc20
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Merge branch 'shapeanalysis'
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2014-05-06 16:49:54 -07:00 |
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Henry Cook
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f8b3117ac0
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bump rocket, uncore
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2014-05-06 13:10:12 -07:00 |
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Henry Cook
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445d4f2eee
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bump rocket, uncore
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2014-05-01 01:46:55 -07:00 |
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Henry Cook
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ce056b4b89
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client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
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Henry Cook
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224e286dd3
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New uncore config objects. Backends get their own file. Simplify fpga uncore.
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2014-04-26 19:46:11 -07:00 |
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Henry Cook
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3d4273954a
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:19:25 -07:00 |
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Henry Cook
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fbf6e44376
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fix connection error in fpga uncore
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2014-04-24 11:58:59 -07:00 |
|
Henry Cook
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1e062d1bcd
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bump rocket, uncore
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2014-04-23 16:27:34 -07:00 |
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Henry Cook
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83a3cb4999
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bump rocket, uncore
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2014-04-22 17:32:39 -07:00 |
|
Yunsup Lee
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2fefbdd453
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fixes to physical design flow
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2014-04-21 21:36:39 -07:00 |
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Henry Cook
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cfd6748318
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patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
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2014-04-21 17:26:33 -07:00 |
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Henry Cook
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1bf5439f0b
|
include new mm test in benchmarks
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2014-04-18 18:05:30 -07:00 |
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Yunsup Lee
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e4c97e7a57
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push tools/tests
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2014-04-14 21:18:22 -07:00 |
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Henry Cook
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691aa4107e
|
bump rocket
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2014-04-14 17:13:57 -07:00 |
|
Henry Cook
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2cb4dbae39
|
Refactored uncore constants and tilelink data
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2014-04-10 13:19:50 -07:00 |
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Henry Cook
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5a5f69bfca
|
finished uncore constant/tilelink data refactor
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2014-04-10 13:13:46 -07:00 |
|
Stephen Twigg
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cac04afc25
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Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL.
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2014-04-08 22:14:16 -07:00 |
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Stephen Twigg
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f643d38672
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Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required)
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2014-04-08 16:50:52 -07:00 |
|
Andrew Waterman
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fb8c7d3da5
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Push rocket
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2014-04-07 23:49:06 -07:00 |
|
Andrew Waterman
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817517c663
|
Better branch prediction
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2014-04-07 16:08:06 -07:00 |
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Henry Cook
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56f515c255
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first steps in uncore constant/tilelink data refactor
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2014-03-30 09:21:08 -07:00 |
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Donggyu Kim
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16274a84b6
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update fpga testbench
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2014-03-21 16:21:15 -07:00 |
|
Yunsup Lee
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8d68ea9e0b
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2014-03-20 01:46:30 -07:00 |
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Yunsup Lee
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7bbcf920be
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sync up master
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2014-03-20 01:45:23 -07:00 |
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Andrew Waterman
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51808d9982
|
Fix minor FP bugs
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2014-03-18 18:37:53 -07:00 |
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Yunsup Lee
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d2c32b048a
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fix bug in htif_fini, need to use vc_handle!
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2014-03-18 01:35:08 -07:00 |
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Andrew Waterman
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0d124d283a
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Write our own vcs main() routine
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2014-03-17 17:02:28 -07:00 |
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Andrew Waterman
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7f23257873
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Print out random seed if test fails
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2014-03-17 15:35:32 -07:00 |
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Andrew Waterman
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fcbbb275aa
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Fix nondeterminism
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2014-03-15 17:35:30 -07:00 |
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Yunsup Lee
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e4b56b5d0e
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generate verilog for rekall
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2014-03-15 15:31:04 -07:00 |
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Andrew Waterman
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b6bf7cfe0c
|
push chisel
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2014-03-11 23:56:57 -07:00 |
|
Andrew Waterman
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7ac003a4f7
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push hardfloat
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2014-03-11 20:36:39 -07:00 |
|
Andrew Waterman
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f04bde75fb
|
New FP encoding
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2014-03-11 19:12:20 -07:00 |
|
Yunsup Lee
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6951333a08
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push rocket
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2014-03-04 23:43:00 -08:00 |
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Andrew Waterman
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d055c0ebaf
|
Push rocket/hardfloat/chisel
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2014-03-04 16:39:06 -08:00 |
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