riscv/rocket-chip
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1513 Commits

Author SHA1 Message Date
Andrew Waterman 9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman 66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman 511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Yunsup Lee fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
 2016-09-07 00:05:00 -07:00
Wesley W. Terpstra d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Yunsup Lee b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) 
now you can add them in any order.  there's an explicit check at the end to figure out whether there are overlapping regions.
 2016-09-06 21:53:55 -07:00
Wesley W. Terpstra aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Yunsup Lee 56d81b0034 fix configstring printout with no memory 2016-09-06 10:40:11 -07:00
Wesley W. Terpstra 54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra 314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra 56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra 3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00
Howard Mao a7f79aa409 get rid of TileLinkMemorySelector 2016-09-04 10:55:19 -07:00
Howard Mao f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper 2016-09-04 10:55:19 -07:00
Howard Mao 66de89c4db allow fixed priority routing in Junctions arbiters 2016-09-04 10:55:19 -07:00
Howard Mao efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types 2016-09-04 10:55:19 -07:00
Howard Mao b9b79e4fb6 get rid of AtoS RTL 2016-09-04 10:55:19 -07:00
Howard Mao f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
Yunsup Lee a4c1942958 flatten Coreplex module hierarchy 2016-09-02 17:45:08 -07:00
Andrew Waterman 63679bb019 Add support for L1 data scratchpads instead of caches 
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
 2016-09-02 16:22:07 -07:00
Jim Lawson dc9ae19936 Work-around for current Scala compiler "structural type loses implicits". 
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.

    [error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
    [error] possible cause: maybe a semicolon is missing before `value asOutput'?
    [error]   }.asOutput
    [error]     ^
    [error] one error found
    [error] (uncore/compile:compileIncremental) Compilation failed

This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
 2016-09-02 15:38:18 -07:00
Andrew Waterman fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
Andrew Waterman e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Andrew Waterman 7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable 2016-09-02 15:27:54 -07:00
Andrew Waterman 6872000f5e Merge pull request #239 from ucb-bar/move_rtc 
Move RTC
 2016-09-02 15:17:49 -07:00
Megan Wachs af364bc7bc Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal 2016-09-02 15:14:39 -07:00
Megan Wachs 8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications 2016-09-02 11:11:40 -07:00
Andrew Waterman c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Yunsup Lee 4a7972be31 connect testharness components via member functions (#236) 
to prevent code duplication for new testbenches
 2016-09-01 18:38:39 -07:00
Howard Mao c66318307c no longer need to set invalidate_lr in RoCC examples 2016-08-31 22:05:35 -07:00
Howard Mao 27c674972c tie off invalidate_lr in RoCC 2016-08-31 22:00:27 -07:00
Howard Mao bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF 2016-08-31 22:00:27 -07:00