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Author SHA1 Message Date
Megan Wachs
7458378a4a RegFieldDesc: Update reg field descs to be more correct for devices. 2018-03-12 08:24:36 -07:00
Megan Wachs
3063fd1b46 RegFieldDesc: update DescribedReg to suppot new features 2018-03-12 08:24:36 -07:00
Megan Wachs
2f239f2a9a RegFieldDesc: Add more features to support more IP-XACT like descriptions & emit them in the JSON 2018-03-12 08:24:36 -07:00
Henry Cook
e07b37c7ad
Merge pull request #1186 from edcote/patch-1 
Update TestDriver module to support FSDB
 2018-03-11 11:40:25 -07:00
Henry Cook
d3c16258fd
Merge pull request #1280 from freechipsproject/reg-desc-anno 
util: use chisel3.core.dontTouch
 2018-03-10 19:50:54 -08:00
Henry Cook
0e0963d360 util: use chisel3.core.dontTouch 2018-03-10 17:04:46 -08:00
Henry Cook
99862942fe
Merge pull request #1276 from freechipsproject/reg-desc-anno 
sbt: bump json4s-jackson to 3.5.3
 2018-03-08 19:04:23 -08:00
Henry Cook
1b93b27da4 util: restore dontTouch annotation; Chisel's is broken on 0 element Aggregates 2018-03-08 16:12:15 -08:00
Schuyler Eldridge
933f2ce958 Bump riscv-tools for riscv-fesvr submodule ptr fix (#1275) 
The riscv-fesvr submodule was pointing at my local version, oops. This
corrects that in an updated version of riscv-tools.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-03-08 14:27:51 -08:00
Henry Cook
d6e2c1a73f more != wire deprecations 2018-03-08 12:36:51 -08:00
Henry Cook
32592377c6 sbt: bump json4s-jackson to 3.5.3 2018-03-08 12:31:52 -08:00
Schuyler Eldridge
8bb397a1b9 Fix VCS argument parsing (#1266) 
* Add +permissive/+permissive-off for VCS args

This adds guards around Verilog/VCS options for VCS calls with HTIF's
new `+permissive`/`+permissive-off` options. This enables HTIF to
permissively parse all options inside one of these guards while not
erroring on unknonw commands. This is necessary for VCS, unlike with the
emulator, as HTIF is giving all commands as opposed to only host and
target arguments (like with Verilator/emulator.cc).

* Bump riscv-tools for fesvr VCS fix

* Bump riscv-rools/riscv-fesvr (VCS stderr fix)

Fixes #1266

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-03-07 22:59:04 -08:00
Megan Wachs
7d146f3401
Merge pull request #1273 from freechipsproject/no_jtag_vpi 
Deprecate JTAGVPI
 2018-03-07 14:50:26 -08:00
Megan Wachs
ef7a6115b7 vsim: don't need VPI without JTAGVPI 2018-03-07 10:58:09 -08:00
Megan Wachs
15dc7f6760 JTAGVPI: remove it from Chisel as it is unused 2018-03-07 10:55:45 -08:00
Megan Wachs
42e614550c JTAGVPI: remove it in favor of remote bitbang 2018-03-07 10:53:49 -08:00
Jack Koenig
64b707cbb6 Bump Chisel and FIRRTL for annotations refactor (#1261) 
Also brings in an autoclonetype enhancement and some bug fixes
 2018-03-07 10:22:38 -08:00
Schuyler Eldridge
d0b46c5b8f Align RoCCIO with new cloneType (#1270) 
- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-03-06 17:53:51 -08:00
Megan Wachs
f1bd9c99aa
Merge pull request #1262 from freechipsproject/beu-regfield 
Add BusErrorUnit RegFieldDesc
 2018-03-06 12:31:00 -08:00
Megan Wachs
f00e9576e3
Merge pull request #1263 from freechipsproject/sim_jtag_reset 
SimJTAG: make the reset/init connectivity more flexible.
 2018-03-06 11:28:51 -08:00
Megan Wachs
b669fb3d6a Merge remote-tracking branch 'origin/master' into beu-regfield 2018-03-06 11:04:17 -08:00
Megan Wachs
2a0e67ab15
Merge pull request #1267 from freechipsproject/plic_source_0 
PLIC: Update RegFieldDesc:  source 0 is different
 2018-03-06 11:03:26 -08:00
Megan Wachs
a3d99e5ba2 DescribedReg: fix some imports 2018-03-06 11:02:10 -08:00
Megan Wachs
a20998e215 SimJTAG: fix verilog typo 2018-03-05 16:27:17 -08:00
Megan Wachs
8856953905 DescribedReg: move to regmapper 2018-03-05 16:12:14 -08:00
Megan Wachs
4256d99a9b PLIC: priority/threshold are really WARL (RWSPECIAL). Explain why. 2018-03-05 16:10:05 -08:00
Megan Wachs
41d1a62713 PLIC: Update RegFieldDesc to reflect the fact that source 0 isn't like all the others 2018-03-05 15:29:14 -08:00
Megan Wachs
bd3a72e585 Merge remote-tracking branch 'origin/master' into sim_jtag_reset 2018-03-05 12:41:39 -08:00
Megan Wachs
e3be5db3e6 BUE: more verbose register descriptions 2018-03-05 12:02:42 -08:00
Megan Wachs
878a357a0d RegFieldDesc: Add utilities for generating and describing registers at the same time. 2018-03-05 12:02:42 -08:00
Megan Wachs
5eae81038d SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two 2018-03-02 17:29:17 -08:00
Andrew Waterman
644ba6dafa Add BusErrorUnit RegFieldDesc 2018-03-02 17:25:13 -08:00
Jack Koenig
8c6e745653
Bump chisel and firrtl (#1232) 
* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
 2018-03-01 15:19:12 -08:00
Henry Cook
20a8876856
Merge pull request #1190 from freechipsproject/bus-api 
BusWrapper API Update
 2018-03-01 01:13:50 -08:00
Megan Wachs
cdd2a9227f
Merge pull request #1256 from freechipsproject/json_emit_enums 
RegFieldDesc: Emit enumerations into JSON if they exist
 2018-02-28 11:32:14 -08:00
Megan Wachs
d13dc8ac2a RegFieldDesc: Emit enumerations if they exist 2018-02-28 09:42:25 -08:00
Andrew Waterman
a48dd575b2
Merge pull request #1254 from freechipsproject/amo-aqrl 
Fix mapping of acquire/release AMOs to fence operations
 2018-02-27 19:49:40 -06:00
Henry Cook
86c10b3cef
Merge pull request #1250 from seldridge/add-jtag-vpi-c-vsim 
Add jtag_vpi.c to sources for vsim
 2018-02-26 15:40:12 -07:00
Schuyler Eldridge
4bcc42550e Remove JTAG vpi from VCS build 
h/t @mwachs5

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-02-26 15:12:18 -05:00
bipult
47d63d6baa
Merge pull request #1251 from freechipsproject/rocket_covers 
Added functional covers
 2018-02-25 09:01:33 -08:00
Andrew Waterman
eb6e192ec0 Fix mapping of acquire/release AMOs to fence operations 
AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO.  These had been swapped.  This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).

Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations.  For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
 2018-02-23 16:39:47 -08:00
Henry Cook
30c0635bb3 subsystem: add some inter-wrapper buffer params 2018-02-23 15:31:18 -08:00
Wesley W. Terpstra
95294bbdcb
PatternPusher: put data at correct address when misaligned (#1249) 2018-02-23 15:20:56 -08:00
Schuyler Eldridge
d0e350976a Add jtag_vpi.c to sources for vsim 
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
 2018-02-23 17:31:24 -05:00
Henry Cook
ad823ef43c subsystem: pbus crossing type 2018-02-23 13:52:18 -08:00
Henry Cook
5725e17969 subsystem: even more general coupler methods 2018-02-23 13:52:12 -08:00
Jacob Chang
87eed645d8
Fix JTAG cover description (#1248) 2018-02-23 12:13:31 -08:00
Henry Cook
5b1d72c776 subsystem: expose HasTiles Parameters 2018-02-22 23:46:08 -08:00
Henry Cook
099bbec666 subsystem: more buswrapper coupling methods 2018-02-22 23:45:21 -08:00
Bipul Talukdar
2e548c9ad2 Added functional covers 2018-02-22 23:20:12 -08:00