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Commit Graph

534 Commits

Author SHA1 Message Date
Yunsup Lee
7fe052e1bf update README 2013-04-24 02:05:28 -07:00
Yunsup Lee
9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
Yunsup Lee
93df795e48 change LLC leaf SRAM size 2013-04-22 11:06:50 -07:00
Andrew Waterman
7f5282d355 replace RDNPC with AUIPC 2013-04-22 04:21:46 -07:00
Huy Vo
2ac3fd5306 get rid of init_node 2013-04-20 01:36:32 -07:00
Huy Vo
0d87e3bacc fixed init pin generation 2013-04-20 00:38:01 -07:00
Henry Cook
a01cdf95fd tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps 2013-04-10 13:53:27 -07:00
Henry Cook
d7982bf27f bump uncore for grant fix 2013-04-09 14:29:49 -07:00
Andrew Waterman
7ea782fd22 add LR/SC 2013-04-07 19:36:15 -07:00
Henry Cook
c6b56c5f25 bump rocket for coherence bug fix 2013-04-04 15:52:20 -07:00
Henry Cook
9d5e97d89e override io in LogicalNetwork 2013-03-28 14:10:20 -07:00
Henry Cook
16ad8a7e9c Fixes after merge 2013-03-25 19:14:38 -07:00
Andrew Waterman
8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
eec590c1bf Added support for multiple L2 banks. Moved tile IO queueing. 2013-03-25 17:01:46 -07:00
Henry Cook
806f897fc4 nTiles -> nClients in LogicalNetworkConfig 2013-03-25 17:01:46 -07:00
Andrew Waterman
ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
cf76665d09 writebacks on release network pass asm tests and bmarks 2013-03-25 17:01:46 -07:00
Henry Cook
a0dc8d52d6 using new network and l2 controller 2013-03-25 17:01:46 -07:00
Andrew Waterman
def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
Andrew Waterman
ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00
Yunsup Lee
bc140ce9bc add vec_{vvadd,cmplxmult,matmul} bmarks 2013-03-19 00:43:51 -07:00
Yunsup Lee
9efe71412f add DRAMSideLLCNull 2013-03-19 00:43:34 -07:00
Andrew Waterman
c6695bee7c fix emulator HTIF interface bug 2013-02-20 16:11:21 -08:00
Andrew Waterman
fc26150933 update to new Mem style 2013-02-20 16:10:47 -08:00
Eric Love
17b8654042 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-02-12 12:47:03 -06:00
Yunsup Lee
61b18a6722 push rocket,hwacha,uncore 2013-02-09 01:05:51 -08:00
Andrew Waterman
dbb61306f0 randomize coreid mapping 2013-01-26 16:13:14 -08:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Yunsup Lee
f37b9d9a7d fix dramsim2 memory model to wrap around
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
2013-01-23 01:40:15 -08:00
Yunsup Lee
217898c7d0 emulator depends on source files in src directory 2013-01-23 01:39:47 -08:00
Yunsup Lee
516a64f576 commit vec=true 2013-01-22 20:24:33 -08:00
Henry Cook
bb5c465bb3 Switched back to old, better-tested hub on master 2013-01-22 19:57:31 -08:00
Henry Cook
5b82d72eb7 New TileLink bundle names 2013-01-21 17:19:07 -08:00
Henry Cook
72bba81a76 now using single-ported coherence master 2013-01-16 23:58:24 -08:00
Henry Cook
e33648532b Refactored packet headers/payloads 2013-01-15 15:57:06 -08:00
Henry Cook
a922b60152 Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor 2013-01-07 14:23:49 -08:00
Henry Cook
f2cef8d8d2 new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore 2013-01-07 14:19:55 -08:00
Andrew Waterman
bbd010750f add missing #include 2013-01-06 04:53:40 -08:00
Andrew Waterman
fd727bf8aa add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
2013-01-06 03:58:10 -08:00
Andrew Waterman
03df2c3766 update .gitignores 2013-01-06 03:58:10 -08:00
Henry Cook
d0805359a5 Refactored uncore conf 2012-12-13 11:46:29 -08:00
Henry Cook
1d7f1a8182 Removed dummy tile instances 2012-12-12 16:44:03 -08:00
Henry Cook
0e73cc8c12 Removed dummy tile instances 2012-12-12 16:41:21 -08:00
Henry Cook
177909c955 Initial version of phys/log network compiles 2012-12-12 11:15:10 -08:00
Henry Cook
be4e5b8327 Initial version of phys/log network compiles 2012-12-12 00:06:14 -08:00
Yunsup Lee
98c0ea9875 push rocket, tests, and vt-libs 2012-12-07 16:59:15 -08:00
Andrew Waterman
10a6a42a4a make vlsi use dram model by default 2012-12-06 03:13:45 -08:00
Andrew Waterman
d911e635d6 simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
Andrew Waterman
5dfb388f03 update to newest rocket 2012-11-27 02:43:31 -08:00
Andrew Waterman
ea7029484e update to latest rocket 2012-11-26 20:57:12 -08:00