Yunsup Lee
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7fe052e1bf
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update README
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2013-04-24 02:05:28 -07:00 |
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Yunsup Lee
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9114012def
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assmebly tests are now built from riscv-tests
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2013-04-24 01:59:14 -07:00 |
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Yunsup Lee
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93df795e48
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change LLC leaf SRAM size
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2013-04-22 11:06:50 -07:00 |
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Andrew Waterman
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7f5282d355
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replace RDNPC with AUIPC
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2013-04-22 04:21:46 -07:00 |
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Huy Vo
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2ac3fd5306
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get rid of init_node
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2013-04-20 01:36:32 -07:00 |
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Huy Vo
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0d87e3bacc
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fixed init pin generation
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2013-04-20 00:38:01 -07:00 |
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Henry Cook
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a01cdf95fd
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tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps
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2013-04-10 13:53:27 -07:00 |
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Henry Cook
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d7982bf27f
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bump uncore for grant fix
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2013-04-09 14:29:49 -07:00 |
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Andrew Waterman
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7ea782fd22
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add LR/SC
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2013-04-07 19:36:15 -07:00 |
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Henry Cook
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c6b56c5f25
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bump rocket for coherence bug fix
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2013-04-04 15:52:20 -07:00 |
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Henry Cook
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9d5e97d89e
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override io in LogicalNetwork
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2013-03-28 14:10:20 -07:00 |
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Henry Cook
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16ad8a7e9c
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Fixes after merge
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2013-03-25 19:14:38 -07:00 |
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Andrew Waterman
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8e926f8d79
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remove aborts
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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eec590c1bf
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Added support for multiple L2 banks. Moved tile IO queueing.
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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806f897fc4
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-25 17:01:46 -07:00 |
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Andrew Waterman
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ce4c1aa566
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remove aborts
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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cf76665d09
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writebacks on release network pass asm tests and bmarks
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2013-03-25 17:01:46 -07:00 |
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Henry Cook
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a0dc8d52d6
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using new network and l2 controller
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2013-03-25 17:01:46 -07:00 |
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Andrew Waterman
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def11e44b8
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don't pipe stdout to vcd2vpd
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2013-03-25 17:01:13 -07:00 |
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Andrew Waterman
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ef4927c9ad
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use a named pipe for VCD -> VPD conversion
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2013-03-25 16:19:19 -07:00 |
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Yunsup Lee
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bc140ce9bc
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add vec_{vvadd,cmplxmult,matmul} bmarks
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2013-03-19 00:43:51 -07:00 |
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Yunsup Lee
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9efe71412f
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add DRAMSideLLCNull
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2013-03-19 00:43:34 -07:00 |
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Andrew Waterman
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c6695bee7c
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fix emulator HTIF interface bug
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2013-02-20 16:11:21 -08:00 |
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Andrew Waterman
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fc26150933
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update to new Mem style
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2013-02-20 16:10:47 -08:00 |
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Eric Love
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17b8654042
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-02-12 12:47:03 -06:00 |
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Yunsup Lee
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61b18a6722
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push rocket,hwacha,uncore
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2013-02-09 01:05:51 -08:00 |
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Andrew Waterman
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dbb61306f0
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randomize coreid mapping
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2013-01-26 16:13:14 -08:00 |
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Andrew Waterman
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4077b22929
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include fesvr as a library; improve harnesses
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2013-01-24 23:57:23 -08:00 |
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Yunsup Lee
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f37b9d9a7d
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fix dramsim2 memory model to wrap around
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
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2013-01-23 01:40:15 -08:00 |
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Yunsup Lee
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217898c7d0
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emulator depends on source files in src directory
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2013-01-23 01:39:47 -08:00 |
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Yunsup Lee
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516a64f576
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commit vec=true
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2013-01-22 20:24:33 -08:00 |
|
Henry Cook
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bb5c465bb3
|
Switched back to old, better-tested hub on master
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2013-01-22 19:57:31 -08:00 |
|
Henry Cook
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5b82d72eb7
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New TileLink bundle names
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2013-01-21 17:19:07 -08:00 |
|
Henry Cook
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72bba81a76
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now using single-ported coherence master
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2013-01-16 23:58:24 -08:00 |
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Henry Cook
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e33648532b
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Refactored packet headers/payloads
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2013-01-15 15:57:06 -08:00 |
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Henry Cook
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a922b60152
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Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
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2013-01-07 14:23:49 -08:00 |
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Henry Cook
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f2cef8d8d2
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new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
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2013-01-07 14:19:55 -08:00 |
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Andrew Waterman
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bbd010750f
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add missing #include
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2013-01-06 04:53:40 -08:00 |
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Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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03df2c3766
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update .gitignores
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2013-01-06 03:58:10 -08:00 |
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Henry Cook
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d0805359a5
|
Refactored uncore conf
|
2012-12-13 11:46:29 -08:00 |
|
Henry Cook
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1d7f1a8182
|
Removed dummy tile instances
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2012-12-12 16:44:03 -08:00 |
|
Henry Cook
|
0e73cc8c12
|
Removed dummy tile instances
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2012-12-12 16:41:21 -08:00 |
|
Henry Cook
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177909c955
|
Initial version of phys/log network compiles
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2012-12-12 11:15:10 -08:00 |
|
Henry Cook
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be4e5b8327
|
Initial version of phys/log network compiles
|
2012-12-12 00:06:14 -08:00 |
|
Yunsup Lee
|
98c0ea9875
|
push rocket, tests, and vt-libs
|
2012-12-07 16:59:15 -08:00 |
|
Andrew Waterman
|
10a6a42a4a
|
make vlsi use dram model by default
|
2012-12-06 03:13:45 -08:00 |
|
Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
|
2012-12-04 07:04:26 -08:00 |
|
Andrew Waterman
|
5dfb388f03
|
update to newest rocket
|
2012-11-27 02:43:31 -08:00 |
|
Andrew Waterman
|
ea7029484e
|
update to latest rocket
|
2012-11-26 20:57:12 -08:00 |
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