Howard Mao
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6fc1e92708
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add option to print cycle count regardless of exit status
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2015-12-04 12:04:13 -08:00 |
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Howard Mao
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f35b83d3ca
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allow configuration of rocket ICache buffering
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2015-12-02 17:18:39 -08:00 |
|
Howard Mao
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ebf2417a32
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rocc-fpu-port merged into master for rocket
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2015-12-02 09:02:43 -08:00 |
|
Howard Mao
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cdc476a370
|
change Rocc parameterization
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2015-12-01 17:56:09 -08:00 |
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Andrew Waterman
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e0d849fec5
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Fix zscale testing
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
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2015-12-01 17:31:48 -08:00 |
|
Andrew Waterman
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5eeb8969f6
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fix zscale build (run still fails)
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2015-12-01 16:20:34 -08:00 |
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Howard Mao
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c8c68e75bb
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base NGenerators on NTiles, not the other way around
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2015-12-01 15:26:09 -08:00 |
|
Howard Mao
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e4043570bd
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bump groundtest and hardfloat
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2015-11-30 18:06:15 -08:00 |
|
Howard Mao
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40d68406d6
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use xlen parameter for ALU
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2015-11-30 18:04:44 -08:00 |
|
Colin Schmidt
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ec4ade988b
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[travis] add multiple configs including rocc
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2015-11-28 07:17:49 -08:00 |
|
Colin Schmidt
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7259239ba4
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Merge pull request #31 from ucb-bar/multirocc
implement support for multiple RoCC accelerators
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2015-11-28 08:56:07 -05:00 |
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Howard Mao
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23f0756978
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implement support for multiple RoCC accelerators
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2015-11-26 12:49:04 -08:00 |
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Andrew Waterman
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e25a020e60
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Construct device tree ROM in MMIO region
Rebuild riscv-tools for this to work!
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2015-11-25 21:23:37 -08:00 |
|
Andrew Waterman
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49d93da87e
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Factor out more common zscale code
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2015-11-24 19:17:21 -08:00 |
|
Andrew Waterman
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52b25c3da0
|
Factor out more common zscale code
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2015-11-24 18:34:03 -08:00 |
|
Andrew Waterman
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1761db3272
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Factor out some common code from zscale
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2015-11-24 18:14:06 -08:00 |
|
Howard Mao
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ec6bfde9a3
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fix WritebackUnit issue in uncore
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2015-11-21 16:11:22 -08:00 |
|
Howard Mao
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9d50f37289
|
fix unused set issue for multiple L2 cache banks
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2015-11-20 23:26:28 -08:00 |
|
Howard Mao
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ad3b7fd0e1
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adjust CacheFillTest configuration
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2015-11-19 10:52:14 -08:00 |
|
Howard Mao
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4806f72b08
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add CacheFillTest to check L2 conflict misses
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2015-11-19 00:16:28 -08:00 |
|
Howard Mao
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3514b6eb87
|
add some more useful configurations
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2015-11-18 22:11:17 -08:00 |
|
Howard Mao
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379d43d5f4
|
make MultiChannel routing more performant
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2015-11-18 22:11:17 -08:00 |
|
Yunsup Lee
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ea8ba49805
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improve memory system: specialize MultiChannel routing
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2015-11-18 21:58:22 -08:00 |
|
Andrew Waterman
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5195a5b891
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Remove IPI network
This is now provided via MMIO.
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2015-11-16 21:53:14 -08:00 |
|
Henry Cook
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485f1b7bd7
|
bump uncore
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2015-11-16 18:14:03 -08:00 |
|
Yunsup Lee
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8916c7e99c
|
push rocket
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2015-11-14 16:43:28 -08:00 |
|
Yunsup Lee
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6a6371fdb6
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move to new version of hardfloat
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2015-11-14 14:50:13 -08:00 |
|
Howard Mao
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a1063bad54
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fix issues with non-allocating put/get
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2015-11-12 15:54:34 -08:00 |
|
Colin Schmidt
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97d0e195ae
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Merge pull request #28 from ucb-bar/yusnup
Don't re-generate the .d files on "make clean"
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2015-11-12 00:46:21 -08:00 |
|
Palmer Dabbelt
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07f0e6be94
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Don't re-generate the .d files on "make clean"
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2015-11-12 00:41:55 -08:00 |
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Howard Mao
|
6ddf81090b
|
didn't mean to turn off GenerateCached in last commit
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2015-11-11 17:39:08 -08:00 |
|
Howard Mao
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11f0b3d8db
|
restore old L2 cache AcquireTransactor configuration
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2015-11-11 17:10:58 -08:00 |
|
Howard Mao
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31da692ccc
|
default to single tile in WithMemtest
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2015-11-11 14:54:13 -08:00 |
|
Howard Mao
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55581195eb
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add groundtest submodule for simple memory testing
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2015-11-11 14:33:02 -08:00 |
|
Howard Mao
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149480411e
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make sure ClientTileLinkEnqueuer uses the correct parameters
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2015-11-10 16:09:19 -08:00 |
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Howard Mao
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51f128ec74
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actually use backendBuffering in front of unwrapper/converter chain
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2015-11-09 11:50:18 -08:00 |
|
Yunsup Lee
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1e772daeea
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no spaces in Makefrag
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2015-11-05 16:42:05 -08:00 |
|
Howard Mao
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cb0c2df051
|
update fpga-zynq
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2015-11-05 10:50:13 -08:00 |
|
Howard Mao
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42e7067400
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bump uncore
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2015-11-05 10:49:25 -08:00 |
|
Howard Mao
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bbf14ddc01
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use definitions in consts header whenever possible
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2015-11-05 10:48:32 -08:00 |
|
Howard Mao
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fb501e75c0
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fixes for sub-block TL requests in uncore
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2015-11-05 10:48:32 -08:00 |
|
Howard Mao
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7b252d8f89
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get rid of now-unnecessary bits in MIF tag
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2015-11-05 10:48:32 -08:00 |
|
Howard Mao
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ba5a6af05c
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correctly stripe data across memory channels in simulation
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2015-11-05 10:48:32 -08:00 |
|
Sagar Karandikar
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ee9195be26
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rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
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2015-11-05 10:48:32 -08:00 |
|
Sagar Karandikar
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354abf5e6b
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fix NSets calculation
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2015-11-05 10:48:32 -08:00 |
|
Howard Mao
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dcef020ca0
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get multichannel simulation working in emulator
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2015-11-05 10:48:32 -08:00 |
|
Howard Mao
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04d92dddbd
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add back decoupled NASTI connection at edge of RocketChip
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2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
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51116e0674
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add 2 and 4 memory channel configs
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2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
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0d245741bc
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add multichannel NASTI support in Verilog testbench
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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9dabcab9c2
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Get rid of MemIO in Top and replace with AXI throughout
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2015-11-05 10:48:32 -08:00 |
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