riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
74796868e7 chisel bump 2014-08-12 10:58:09 -07:00
Henry Cook
0ca24a5d91 fix debug flags 2014-08-12 10:35:39 -07:00
Henry Cook
7f07771600 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Scott Beamer
d3a8a224fe README updated for new fpga flow 2014-08-07 14:52:56 -07:00
Scott Beamer
e390eba8ce convert README to markdown 2014-08-07 14:50:31 -07:00
Scott Beamer
4109d7cc87 newest version of chisel needed for brams 2014-08-07 13:49:31 -07:00
Palmer Dabbelt
0fc3acb978 Update the directions on how to update Chisel 
It seems that the update process in the README is really out of date
(it refers to scala-2.8 and chisel-1.1).  I've updated it to what I
believe to be correct, which now just consists of pulling the Chisel
submodule.

Note that I tried this myself, but when I did it I also ran an "sbt
package" in the Chisel submodule top-level directory (there's no "sbt"
directory in there any more).  I believe it's not necessary to run
"sbt package", but I really know nothing about SBT...
 2014-08-05 11:56:03 -07:00
Palmer Dabbelt
693489da87 Add a note to the README about "make emulator-debug" 
I made a clean checkout of reference-chip yesterday and wasn't able to
build the debug emulator without first having built the non-debug
emulator.  I just added a note to the README to say this.
 2014-08-05 11:53:55 -07:00
Adam Izraelevitz
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Adam Izraelevitz
fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	src/main/scala/ReferenceChip.scala
 2014-08-01 18:07:22 -07:00
Henry Cook
434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Stephen Twigg
d2a3b1dc20 Merge branch 'shapeanalysis' 2014-05-06 16:49:54 -07:00
Henry Cook
f8b3117ac0 bump rocket, uncore 2014-05-06 13:10:12 -07:00
Henry Cook
445d4f2eee bump rocket, uncore 2014-05-01 01:46:55 -07:00
Henry Cook
ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00
Henry Cook
fbf6e44376 fix connection error in fpga uncore 2014-04-24 11:58:59 -07:00
Henry Cook
1e062d1bcd bump rocket, uncore 2014-04-23 16:27:34 -07:00
Henry Cook
83a3cb4999 bump rocket, uncore 2014-04-22 17:32:39 -07:00
Yunsup Lee
2fefbdd453 fixes to physical design flow 2014-04-21 21:36:39 -07:00
Henry Cook
cfd6748318 patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) 2014-04-21 17:26:33 -07:00
Henry Cook
1bf5439f0b include new mm test in benchmarks 2014-04-18 18:05:30 -07:00
Yunsup Lee
e4c97e7a57 push tools/tests 2014-04-14 21:18:22 -07:00
Henry Cook
691aa4107e bump rocket 2014-04-14 17:13:57 -07:00
Henry Cook
2cb4dbae39 Refactored uncore constants and tilelink data 2014-04-10 13:19:50 -07:00
Henry Cook
5a5f69bfca finished uncore constant/tilelink data refactor 2014-04-10 13:13:46 -07:00
Stephen Twigg
cac04afc25 Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL. 2014-04-08 22:14:16 -07:00
Stephen Twigg
f643d38672 Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required) 2014-04-08 16:50:52 -07:00
Andrew Waterman
fb8c7d3da5 Push rocket 2014-04-07 23:49:06 -07:00
Andrew Waterman
817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Henry Cook
56f515c255 first steps in uncore constant/tilelink data refactor 2014-03-30 09:21:08 -07:00
Donggyu Kim
16274a84b6 update fpga testbench 2014-03-21 16:21:15 -07:00
Yunsup Lee
8d68ea9e0b Merge branch 'master' of github.com:ucb-bar/reference-chip 2014-03-20 01:46:30 -07:00
Yunsup Lee
7bbcf920be sync up master 2014-03-20 01:45:23 -07:00
Andrew Waterman
51808d9982 Fix minor FP bugs 2014-03-18 18:37:53 -07:00
Yunsup Lee
d2c32b048a fix bug in htif_fini, need to use vc_handle! 2014-03-18 01:35:08 -07:00
Andrew Waterman
0d124d283a Write our own vcs main() routine 2014-03-17 17:02:28 -07:00
Andrew Waterman
7f23257873 Print out random seed if test fails 2014-03-17 15:35:32 -07:00
Andrew Waterman
fcbbb275aa Fix nondeterminism 2014-03-15 17:35:30 -07:00
Yunsup Lee
e4b56b5d0e generate verilog for rekall 2014-03-15 15:31:04 -07:00
Andrew Waterman
b6bf7cfe0c push chisel 2014-03-11 23:56:57 -07:00
Andrew Waterman
7ac003a4f7 push hardfloat 2014-03-11 20:36:39 -07:00
Andrew Waterman
f04bde75fb New FP encoding 2014-03-11 19:12:20 -07:00
Yunsup Lee
6951333a08 push rocket 2014-03-04 23:43:00 -08:00
Andrew Waterman
d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Yunsup Lee
23045ec379 add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv 2014-03-02 03:38:06 -08:00