riscv/rocket-chip
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246 Commits

Author SHA1 Message Date
Wesley W. Terpstra
30f1f1e7c7 rocket: turn on early ack for DTIM 2017-05-01 22:53:41 -07:00
Andrew Waterman
d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Andrew Waterman
7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR 2017-04-27 19:50:38 -07:00
Henry Cook
3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Andrew Waterman
99de42d34c Swap order of ITIM WidthWidget and Fragmenter 
e99fa057ac accidentally reversed them
 2017-04-27 15:30:02 -07:00
Andrew Waterman
8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
 2017-04-27 15:16:29 -07:00
Henry Cook
e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman
80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Wesley W. Terpstra
f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) 2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) 
* dcache: put a flow Q to absorb back-pressure without restarting pipeline

When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.

* dcache: provision as few stages as possible
 2017-04-24 23:28:04 -07:00
Wesley W. Terpstra
9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) 
@aswaterman it's in
 2017-04-24 19:12:37 -07:00
Andrew Waterman
65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" 2017-04-24 02:01:15 -07:00
Andrew Waterman
36a7971975 Bypass scoreboard to reduce MMIO latency 2017-04-24 02:01:15 -07:00
Andrew Waterman
f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew Waterman
c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew Waterman
d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Megan Wachs
c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Andrew Waterman
67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory 2017-04-20 08:47:03 -07:00
Andrew Waterman
d82a0dc231 Mitigate D$ exception critical path, yet again 2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d Only report D$ exceptions on not-nacked accesses 2017-04-18 00:47:58 -07:00
Andrew Waterman
a956b78dd2 In TLBPermissions, merge across some region types 
We only care whether they have side effects or not.
 2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894 Pipeline D$ exception response into s2 2017-04-18 00:47:58 -07:00
Andrew Waterman
cc9ec1d51a Send D$ grant acks early; accept release acks early 
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
 2017-04-18 00:47:58 -07:00
Andrew Waterman
728569c717 Reduce access-exception generation critical path 2017-04-18 00:47:58 -07:00
Andrew Waterman
c366007a0d Tighten PMAs for LR/SC and misaligned accesses 
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
 2017-04-18 00:47:58 -07:00
Andrew Waterman
74a7838de0 In TLBPermissions, don't merge regions of different types 2017-04-18 00:47:58 -07:00
Andrew Waterman
7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew Waterman
debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew Waterman
a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Andrew Waterman
fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) 
* only replicate scratch slave d-channel resp when AMO req

* dtim: port can't support put partial mask with holes

* dtim: use \!isRead instead of isAMO

* Fix ScratchpadSlavePort looking at wrong Acquire message

Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
 2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf Unconditionally write badaddr, possibly to zero 
59d33f6b83
 2017-04-12 13:35:02 -07:00
Andrew Waterman
470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew Waterman
a43bf2feae Add vectored interrupt support 
4dcaa944ba

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

ba6d88466a
 2017-04-08 00:29:45 -07:00
Andrew Waterman
c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00