.. |
ALU.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
Arbiter.scala
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Pipeline D$ exception response into s2
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2017-04-18 00:47:58 -07:00 |
Breakpoint.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
BTB.scala
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Update RAS speculatively from fetch stage
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2017-04-24 02:01:15 -07:00 |
Consts.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
CSR.scala
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Use correct interrupt priority order
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2017-04-24 02:01:15 -07:00 |
DCache.scala
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Mitigate D$ exception critical path, yet again
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2017-04-18 00:47:58 -07:00 |
Decode.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
Events.scala
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Add performance counter facility
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2017-03-09 13:58:50 -08:00 |
Frontend.scala
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Update RAS speculatively from fetch stage
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2017-04-24 02:01:15 -07:00 |
HellaCache.scala
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Pipeline D$ exception response into s2
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2017-04-18 00:47:58 -07:00 |
IBuf.scala
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Don't stall the frontend, making it easier to add more features later
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2017-04-24 02:01:15 -07:00 |
ICache.scala
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Don't stall the frontend, making it easier to add more features later
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2017-04-24 02:01:15 -07:00 |
IDecode.scala
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Support SFENCE.VMA rs1 argument
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2017-03-24 16:39:52 -07:00 |
Instructions.scala
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rocket: separate page faults from physical memory access exceptions
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2017-03-27 16:37:09 -07:00 |
Multiplier.scala
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Support unrolling the integer divider
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2017-03-09 11:29:51 -08:00 |
NBDcache.scala
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Mitigate D$ exception critical path, yet again
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2017-04-18 00:47:58 -07:00 |
Package.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
PMP.scala
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Make PMP tolerant to PA size << VA size
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2017-04-17 10:28:33 -07:00 |
PTW.scala
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Pipeline D$ exception response into s2
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2017-04-18 00:47:58 -07:00 |
Rocket.scala
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Update RAS speculatively from fetch stage
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2017-04-24 02:01:15 -07:00 |
RVC.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
ScratchpadSlavePort.scala
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Several ScratchpadSlavePort bug fixes (#676)
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2017-04-13 23:25:51 -07:00 |
SimpleHellaCacheIF.scala
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Pipeline D$ exception response into s2
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2017-04-18 00:47:58 -07:00 |
Tile.scala
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Down with any require() statement that makes me RTFC
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2017-04-21 15:44:42 -07:00 |
TLB.scala
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When not using a cache, LR/SC isn't legal even on cacheable memory
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2017-04-20 08:47:03 -07:00 |
TLBPermissions.scala
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In TLBPermissions, merge across some region types
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2017-04-18 00:47:58 -07:00 |