riscv/rocket-chip
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rocket-chip/src/main/scala/rocket
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Andrew Waterman 8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
..
ALU.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
Arbiter.scala
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Breakpoint.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
BTB.scala
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00
Consts.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
CSR.scala
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
DCache.scala
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
Decode.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
Events.scala
Add performance counter facility
2017-03-09 13:58:50 -08:00
Frontend.scala
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
HellaCache.scala
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
IBuf.scala
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
ICache.scala
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
IDecode.scala
Support SFENCE.VMA rs1 argument
2017-03-24 16:39:52 -07:00
Instructions.scala
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
Multiplier.scala
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
NBDcache.scala
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
Package.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
PMP.scala
Express PMP mask generation with incrementer, not adder
2017-04-27 15:16:29 -07:00
PTW.scala
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Rocket.scala
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
RVC.scala
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
ScratchpadSlavePort.scala
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
SimpleHellaCacheIF.scala
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Tile.scala
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
TLB.scala
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
TLBPermissions.scala
In TLBPermissions, merge across some region types
2017-04-18 00:47:58 -07:00