solomatnikov
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
Henry Cook
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
Henry Cook
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
Henry Cook
46751bedeb
config: MapParameters are back in style
2018-01-30 11:52:44 -08:00
Jacob Chang
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
Andrew Waterman
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
Andrew Waterman
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
...
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
Andrew Waterman
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
Jacob Chang
a749326deb
Add cover points to registers ( #1208 )
2018-01-24 21:37:24 -08:00
Andrew Waterman
7a0252fdfc
Add some covers for FPU structural hazards
2018-01-23 16:32:03 -08:00
Andrew Waterman
a2ca82f92c
Add VM covers
2018-01-23 16:13:35 -08:00
Wesley W. Terpstra
c32150b994
ResetCatchAndSync: work also in the context of a RawModule ( #1202 )
2018-01-19 19:45:52 -08:00
Wesley W. Terpstra
f6f5606f8e
diplomacy: run user instantiate() method after nodes are initialized ( #1198 )
2018-01-18 14:57:47 -08:00
Henry Cook
5cc1411e14
Merge pull request #1199 from freechipsproject/require-messages
...
rocket: add address to tlb permissions require msgs
2018-01-18 14:53:25 -08:00
Jack Koenig
bf5dd6dac3
Replace Parameters in cover with globally setable implementation ( #1200 )
...
This change is made in anticipation of a proper coverage library
2018-01-18 14:45:36 -08:00
Henry Cook
24c1235500
rocket: add address to tlb permissions require msgs
2018-01-18 10:31:51 -08:00
Wesley W. Terpstra
5854fb5f7c
SourceShrinker improvements ( #1197 )
...
* SourceShrinker: preserve FIFO guarantees of slaves
* tilelink: document that Releases can use TtoT, BtoB, and NtoN
TtoT is needed for write-through caches.
2018-01-17 18:02:19 -08:00
Megan Wachs
338e453a91
JTAG: Use new withClock way of overriding clocks ( #1072 )
...
* JTAG: Use new withClock way of overriding clocks
the override clock way is deprecated
* JTAG: use withClock instead of override clock
* JTAG: extend Module for ClockedCounter
* JTAG: Don't use deprecated clock constructs
* JTAG: Remove another override_clock
* Rename "NegativeEdgeLatch"
because it's not a latch, it's just a register on the negative edge of the clock.
* Use the appropriately named NegEdgeReg
* JTAG: Rename another NegativeEdgeLatch
2018-01-17 13:59:05 -08:00
Jacob Chang
80ca018e3a
Add cover points for BusErrorUnit ( #1193 )
2018-01-15 18:00:29 -08:00
Megan Wachs
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
Henry Cook
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
...
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
pentin-as
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
...
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
Henry Cook
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
Henry Cook
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
Henry Cook
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
Albert Huntington
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
...
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
Megan Wachs
a530646d15
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-08 09:11:27 -08:00
Henry Cook
4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port
...
Fix TL MMIO port
2018-01-05 20:37:44 -08:00
Megan Wachs
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
Albert Huntington
8425086f98
Allow rwReg to pass name and description to RegField for documentation.
2018-01-05 16:59:58 -08:00
Megan Wachs
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
Megan Wachs
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
...
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
Henry Cook
b77b93b0b4
util: dontTouchPortsExcept
2018-01-05 14:06:00 -08:00
Andrew Waterman
000cde2f8a
Make ErrorDevice UNCACHEABLE instead of UNCACHED
...
...even though it still supports Acquire. This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00
Andrew Waterman
ad0b9a0b1b
Reduce cases in which FENCE.I must flush D$
...
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
Henry Cook
4853d1355f
rocket: dontTouch HellaCache.io.cpu.resp
2018-01-05 12:50:24 -08:00
Henry Cook
847efde385
coreplex: dontTouch the tile_inputs wire
2018-01-05 12:47:41 -08:00
Wesley W. Terpstra
f749e986cf
coreplex: fix TL MMIO port example
2018-01-05 12:29:47 +01:00
Andrew Waterman
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
...
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
Andrew Waterman
ee1a9485df
Enforce physical-address canonicalization
...
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
Andrew Waterman
7c9a1b0265
Correctly check for virtual-address canonicalization
...
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
Henry Cook
320900f76c
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
Henry Cook
b0e1bc3071
tile: cake reduction
...
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
Henry Cook
efe7165b54
tile: BaseTile refactor, pt 2
...
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
Henry Cook
1579ddb97e
tile: removed RocketTileWrapper. RocketTile now HasCrossing.
2017-12-28 14:00:13 -08:00
Henry Cook
1cd018546c
tile: BaseTile refactor, pt 1
...
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
Henry Cook
ba6dd160a3
diplomacy: allow access to sram Device info
2017-12-22 19:00:43 -08:00
Henry Cook
d9c5ec4f7b
coreplex: HasTiles supplies def tileParams
2017-12-20 17:18:55 -08:00
Henry Cook
ddaeedf2d0
coreplex: make HasTiles more generic
...
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
Henry Cook
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )" ( #1162 )
...
This reverts commit a542ae687e
.
2017-12-19 12:16:26 -08:00