Yunsup Lee and GitHub
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Yunsup Lee and GitHub
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
Yunsup Lee and GitHub
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
Yunsup Lee and GitHub
cf75c2049d
Merge pull request #878 from freechipsproject/fix-fifofixer
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tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 20:22:16 -07:00
Yunsup Lee
21954c1c73
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 19:38:27 -07:00
Yunsup Lee and GitHub
6124bf0cc2
sort entires in the printed address map ( #773 )
2017-05-31 07:45:46 -10:00
Yunsup Lee and GitHub
431e726c29
Merge pull request #727 from ucb-bar/fix-axi2tl-timeout
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Wes's fix for AXI2TL timeout when writes backed up
2017-05-04 01:42:48 -07:00
Yunsup Lee and GitHub
1ecd63611f
Merge pull request #718 from ucb-bar/dtim-putpartial
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Add PutPartial support to DTIM
2017-05-02 15:42:28 -07:00
Yunsup Lee and GitHub
71eaed7d60
Merge pull request #675 from ucb-bar/debug_no_preexec
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More Debug Updates to bring in line with spec
2017-04-18 03:10:27 +09:00
Yunsup Lee
1ad5ef7aa2
bump chisel
2017-04-17 10:28:33 -07:00
Yunsup Lee
aad4f350bf
bump tools
2017-04-17 10:28:33 -07:00
Yunsup Lee and Andrew Waterman
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
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* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
Yunsup Lee and GitHub
716533f77f
Merge pull request #643 from ucb-bar/update-pmp-encoding
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bump riscv-tools
2017-03-31 20:52:49 -07:00
Yunsup Lee
983a561720
bump riscv-tools
2017-03-31 19:20:08 -07:00
Yunsup Lee and Wesley W. Terpstra
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
Yunsup Lee and Wesley W. Terpstra
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
Yunsup Lee and GitHub
18d100c2b5
Merge pull request #461 from ucb-bar/sifive-copyright
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Sifive copyright
2016-11-28 15:25:33 -08:00
Yunsup Lee and GitHub
549e006988
Merge pull request #451 from ucb-bar/more-configs
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More configs
2016-11-24 09:44:52 -08:00
Yunsup Lee and GitHub
42b40130e2
Merge pull request #443 from ucb-bar/tl2-tlb
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Tl2 tlb
2016-11-21 22:00:30 -08:00
Yunsup Lee and Yunsup Lee
23c8b06d4a
use $urandom as seed for $random
2016-10-03 17:56:30 -07:00
Yunsup Lee and Yunsup Lee
62954d543e
correctly initialize the active flag
2016-10-03 17:56:30 -07:00
Yunsup Lee and Yunsup Lee
5ff3d3d61c
correctly initialize with seed
2016-10-02 17:31:32 -07:00
Yunsup Lee and Yunsup Lee
0924f8adb0
print out assigned inerrupt ranges
2016-09-29 11:59:32 -07:00
Yunsup Lee and Yunsup Lee
4c3e8ec1b4
assign interrupt ranges deterministically
2016-09-29 11:59:32 -07:00
Yunsup Lee
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd
rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Yunsup Lee
1b26d78114
correctly print out the addrmap overlapping error message
2016-09-19 13:34:58 -07:00
Yunsup Lee
97809b183f
refactor unittest framework
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as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
Yunsup Lee
710f1ec020
Move BootROM from Coreplex to Periphery
2016-09-14 16:09:59 -07:00
Yunsup Lee
d985cdfc66
Merge branch 'master' into refactor-periphery
2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061
let GlobalAddrMap and ConfigString overridable
2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d
now able to add periphery devices through traits
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Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
Yunsup Lee
2c000a99da
compartmentalize Top into periphery traits
2016-09-08 02:08:57 -07:00
Yunsup Lee
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
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This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Yunsup Lee
a4c1942958
flatten Coreplex module hierarchy
2016-09-02 17:45:08 -07:00
Yunsup Lee and Palmer Dabbelt
3ce8dbb6e5
fix make error mixing implicit and normal rules
2016-06-14 11:59:20 -07:00
Yunsup Lee
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
Yunsup Lee
4afc9c69a0
streamline sbt
2016-04-19 14:22:22 -07:00
Yunsup LeeandGitHub
