riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,243 Commits 1 Branch 0 Tags
44fb3be7d0ed724e7547a2f83bf1204de0294d52
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. TerpstraandGitHub ed38787c36 Merge pull request #622 from ucb-bar/priv-1.10 
Various priv-1.10 changes
 2017-03-27 19:28:30 -07:00
Wesley W. Terpstra 5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra 75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra 4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Wesley W. TerpstraandGitHub 722b0d521f bootrom: also setup SBI a0+a1 for when we hang (#617) 
This way a program started by the debugger still has the DTB handy.
 2017-03-27 00:01:05 -07:00
Wesley W. TerpstraandGitHub 986e1754be Merge pull request #611 from ucb-bar/expose-back-side-bus 
rename l2FrontendBus as fsb, expose bsb
 2017-03-24 23:32:50 -07:00
Wesley W. Terpstra 537274b645 coreplex: move buffers inside the coreplex 
This should make hierarchical place and route easier.
 2017-03-24 22:54:48 -07:00
Wesley W. TerpstraandGitHub 19485a9861 Merge pull request #609 from ucb-bar/dtb-rom 
DTB in the bootrom
 2017-03-24 21:54:13 -07:00
Wesley W. Terpstra e74226564c travis: add dependency on device-tree-compiler 2017-03-24 20:59:33 -07:00
Wesley W. Terpstra f36b1766f8 TLROM: use the smallest ROM implementation that works 
The contents everywhere else are still zero.
 2017-03-24 20:40:28 -07:00
Wesley W. Terpstra ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra 34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra 9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00
Wesley W. TerpstraandGitHub bd08f10816 tilelink2: make sink ids optional (#607) 
* tilelink2: make sink ids optional

* CacheCork: add a special-case for 1 sink id
 2017-03-23 18:19:04 -07:00
Wesley W. TerpstraandGitHub 19eb9b6906 l1tol2: put a flow Q on the exits (#606) 
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
 2017-03-23 16:28:32 -07:00
Wesley W. TerpstraandGitHub 4f78eafbdf Merge pull request #602 from ucb-bar/tl-mmio-pipeline 
TL pipeline MMIO
 2017-03-21 14:59:11 -07:00
Wesley W. Terpstra 4c00066746 rocket: describe dcache as two clients (fifo+cached) 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 81d717e82f coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 198afddb4b tilelink2: add the FIFOFixer 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 930438adba tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra fd521c56a6 tilelink2: add client-side FIFO parameterization 2017-03-21 11:16:51 -07:00
Wesley W. TerpstraandGitHub d4c9c13fb4 Merge pull request #600 from ucb-bar/monitor-spec 
Update monitor spec
 2017-03-20 15:23:34 -07:00
Wesley W. Terpstra 4eef317e84 RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra 431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra 04892fea01 Monitor: support early ack 2017-03-20 14:49:19 -07:00
Wesley W. Terpstra 278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Wesley W. Terpstra 778e189bba Monitor: ProbeAckData and ReleaseData may carry an error 2017-03-20 11:44:13 -07:00
Wesley W. Terpstra 48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
Wesley W. TerpstraandGitHub 5a50acfd9d Merge pull request #595 from ucb-bar/ignore-tl-c 
Ignore TL-C
 2017-03-19 18:49:11 -07:00
Wesley W. Terpstra 0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Wesley W. Terpstra c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
Wesley W. Terpstra 7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
Wesley W. TerpstraandGitHub a4ca424a22 AHBToTL: finally get the error signal right? (#594) 2017-03-18 22:24:20 -07:00
Wesley W. TerpstraandGitHub d4272db067 travis: only run 4 jobs at once (#593) 
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
 2017-03-18 04:14:50 -07:00
Wesley W. TerpstraandGitHub f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) 2017-03-17 19:34:40 -07:00
Wesley W. TerpstraandGitHub db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Wesley W. TerpstraandGitHub eb953c40f0 Merge pull request #587 from ucb-bar/ahb-fix 
ahb: rewrote TLToAHB to avoid retracting requests on stall
 2017-03-16 20:55:39 -07:00
Wesley W. Terpstra 9b5b3279a6 AHBToTL: don't report error during idle cycles 2017-03-16 18:18:29 -07:00
Wesley W. Terpstra 5efd38bf97 apb: put both aFlow options under regression 2017-03-16 15:36:14 -07:00
Wesley W. Terpstra 882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
Wesley W. Terpstra e31b84af33 axi4: use common BufferParams 2017-03-16 15:32:17 -07:00
Wesley W. Terpstra ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Wesley W. Terpstra 778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
Wesley W. Terpstra 963d244094 unittest: try both aFlow settings of TLToAHB 2017-03-16 15:13:57 -07:00
Wesley W. Terpstra 604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
Wesley W. Terpstra bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
Wesley W. TerpstraandGitHub 625919722c Merge pull request #584 from ucb-bar/ahb-in 
AHB master port support
 2017-03-14 19:28:09 -07:00
Wesley W. Terpstra c95c2ca9c8 AHB: include bridge unit tests 2017-03-14 18:34:21 -07:00
Wesley W. Terpstra 0c5fd76089 ahb: implement a ToTL bridge 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 7f71df0925 apb: better test coverage 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 5885bf29b5 axi4: improve test harness 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra d98fd942f1 tilelink2: optimize the supportsX check circuits 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 3c5c877409 tilelink2: make TLBuffer API more flexible 2017-03-14 14:06:18 -07:00
Wesley W. Terpstra 6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing 
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
 2017-03-14 14:06:17 -07:00
Wesley W. TerpstraandAndrew Waterman c847559853 TLB: add a helper API to determine homogeneous page permissions 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra eaf474a081 LFSR: use random intial value of the start register 
We just need to make sure it doesn't initialize randomly stuck at 0.
 2017-03-13 13:17:52 -07:00
Wesley W. Terpstra d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra 0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Wesley W. TerpstraandGitHub 43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Wesley W. Terpstra 676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra 1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra 0178248551 diplomacy: evaluate ResourceBindings only once 2017-03-03 02:04:17 -08:00
Wesley W. Terpstra 8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra 7660be039c rocketchip: add WithTimebase to set RTC frequency 2017-03-03 00:47:50 -08:00
Wesley W. Terpstra 57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
Wesley W. TerpstraandGitHub 46369850cf Merge pull request #567 from ucb-bar/dts 
Dts - Device Tree Output
 2017-03-02 21:51:51 -08:00
Wesley W. Terpstra 4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra 7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra e322692d16 diplomacy: add DeviceTree renderer 2017-03-02 21:19:14 -08:00
Wesley W. Terpstra c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet 2017-03-02 11:14:28 -08:00
Wesley W. Terpstra bb70b1a3c3 diplomacy: add resource tracking 2017-03-02 11:14:28 -08:00
Wesley W. TerpstraandGitHub fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Wesley W. Terpstra c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra 735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Wesley W. TerpstraandGitHub 6ea35125d4 Merge pull request #556 from ucb-bar/rational-config 
Rational config
 2017-02-17 20:31:56 +01:00
Wesley W. Terpstra 9153a9a733 ClockDivider: add docs to appease the reviewer 
... even though this means a delay of 1:30 hours :(
 2017-02-17 19:35:08 +01:00
Wesley W. Terpstra 3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Wesley W. Terpstra 5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra 91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) 
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
 2017-02-17 14:26:23 +01:00
Wesley W. Terpstra 924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra bb334a2cf5 util: add fast2slow direction option to rational crossings 
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
 2017-02-17 13:59:51 +01:00
Wesley W. Terpstra e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. TerpstraandGitHub abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Wesley W. TerpstraandGitHub 69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) 2017-02-04 15:59:50 -08:00
Wesley W. TerpstraandGitHub 71f2445c62 Merge pull request #546 from ucb-bar/dev-zero 
Dev zero
 2017-02-03 19:49:56 -08:00
Wesley W. Terpstra d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
Wesley W. Terpstra b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip 
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
 2017-02-03 17:19:21 -08:00