5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
fd5e00fed9
[coreplex] rename Testing.scala -> RocketTestSuite.scala
2016-09-21 17:35:39 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
ed91e9a89b
Merge remote-tracking branch 'origin' into testharness-refactor
2016-09-20 13:03:21 -07:00
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
644f8fe974
rocketchip: switch to TL2 mmio + port PRCI
2016-09-15 21:28:56 -07:00
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
be9ddae77f
make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
2016-09-15 13:04:01 -07:00
c6f252a913
Remove Option from success flag in coreplex; just use a sane default.
2016-09-15 12:19:22 -07:00
49863944c4
merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
2016-09-14 21:36:27 -07:00
f5db83a72f
NTiles should not be a Knob
2016-09-14 21:16:54 -07:00
e404bea2ee
Merge branch 'master' into move-bootrom
2016-09-14 18:58:48 -07:00
97809b183f
refactor unittest framework
...
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
710f1ec020
Move BootROM from Coreplex to Periphery
2016-09-14 16:09:59 -07:00
565444c40e
Make UnitTestCoreplex cope with an external MMIO network
2016-09-14 12:19:21 -07:00
c3ddff809b
Move PRCI from Coreplex to always-on block, where it belongs
2016-09-14 11:01:05 -07:00
5566bf1b13
Don't route PLIC interrupts through PRCI
...
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
61cbe6164d
Add option to execute JAL from decode stage
...
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
266a2f24bd
Disable Mul early out by default if XLen == 32
...
With a default unroll of 8, it doesn't help performance, but costs area.
2016-09-12 16:50:08 -07:00
f3cdeb08c6
pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 12:40:10 -07:00
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
254f49093c
only use companion objects for types
2016-09-07 12:32:34 -07:00
70cfd7ce13
Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
...
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
f34843f1b9
fix assignment of incoherent vector
2016-09-04 10:12:16 -07:00
a4c1942958
flatten Coreplex module hierarchy
2016-09-02 17:45:08 -07:00
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
fb50f7c9dd
Set default TileLink width to XLen
2016-09-02 15:27:54 -07:00
6872000f5e
Merge pull request #239 from ucb-bar/move_rtc
...
Move RTC
2016-09-02 15:17:49 -07:00
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
8dbee2b133
Don't conditionalize running bmarks on UseVM
2016-08-29 13:43:29 -07:00
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
9ca82dd397
reset default MulDiv config to moderately fast default
...
Closes #228 .
In commit 3f8c60bbd6
2016-08-29 12:31:52 -07:00
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
22ffe36258
Add a queue for timing QoR between L2->MMIO network ( #217 )
2016-08-19 22:51:49 -07:00
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
