Commit Graph
20 Commits
Author SHA1 Message Date
Huy Vo 387cf0ebe0 reset -> resetVal, getReset -> reset 2013-08-12 20:51:54 -07:00
Huy Vo 1864e41361 memserdes + slowio out of rocket and into uncore 2012-10-10 15:25:24 -07:00
Huy Vo fe21142972 fixed memdessert unpacking 2012-10-09 13:03:17 -07:00
Huy Vo e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Huy Vo d9cb96c0ae factored out common stuff to ChiselUtil 2012-09-27 22:53:34 -07:00
Huy Vo db91c4cf6c hwacha 2012-07-27 18:13:20 -07:00
Huy Vo 32a16d183f consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false 2012-07-27 18:13:20 -07:00
Huy Vo 0a97d6ab4d type casting 2012-07-18 13:03:35 -07:00
Huy Vo fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo a99cebb483 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo 04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo c975c21e44 views removed 2012-06-06 12:51:26 -07:00
Huy Vo 7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Huy Vo 181b20d69c working vec unit with pvfb 2012-05-24 10:38:14 -07:00
Huy Vo c9c3bd02bc kill mem stage if fpu nacks in mem stage 2012-04-01 17:02:32 -07:00
Huy Vo c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Huy Vo fdffb124e3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo 6fd1527476 fix to rocket vec_dpath, updating makefiles to run xcpt test cases 2012-03-13 12:34:02 -07:00
Huy Vo 93f41d3359 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo 5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00