Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
9d77e34bee
tilelink2 Filter: make transfer cap robust against large filters
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b
tilelink2 Broadcast: support "bufferless" implementation
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4
tilelink2 Broadcast: only support caching readable devices
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
0f3947bb86
tilelink2 Broadcast: add special case handling for 0 cached clients
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb
tilelink2: Filter adapter removes some of the address space
2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b
tilelink2: broadcast coherence manager
2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d
tilelink2 Parameters: sinkId is per port, not per manager
2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
ed4224dde4
tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull
...
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
a12fea51e8
Plic: skip reserved interrupt in interrupt map printout
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c
tilelink2 HintHandler: delay answers to help TL1 legacy clients
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d2e9fa8ec6
Plic: remove path from ready to bits
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7
Debug: mark the debug device executable
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
89139a9492
Plic: split constants from variables used in config string
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
Megan Wachs
5090ff945b
DebugModule: Be more paranoid about addressing corner cases.
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
Megan Wachs
10d084b9f3
DebugModule: Use the power of RegisterRouter to simplify the DebugROM code.
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236
DebugModule: translate to TL2 with {32,64}-bit XLen width
2016-10-31 11:41:18 -07:00
Howard Mao
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
Andrew Waterman
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
Howard Mao
900a7bbcf1
add PutAtomic support to width adapter
2016-10-26 09:58:26 -07:00
Wesley W. Terpstra
fee67c4abf
diplomacy: add methods to find {out,in}ner-most common node
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548
tilelink2 ToAXI4: use helper method for a_last ( #418 )
2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958
tilelink2 Parameters: fix {contains,supports}Safe ( #416 )
...
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
Wesley W. Terpstra
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
Wesley W. Terpstra
7c334e3c34
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3
axi4 ToTL: handle bad AXI addresses
2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f
axi4: Test ToTL
2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a
axi4: prototype ToTL adapter
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f
axi4 Bundles: add a size calculation helper
...
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9
tilelink2 Isolation: cross the valid signals as well
...
Refactor the code to be less copy-pasty
2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
ac0bb841da
AsyncQueue: cope with far reset propagation delay
2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3
tilelink2 Crossing: these asserts should be done by the AsyncQueue
2016-10-14 16:54:09 -07:00