a35388bc27
fix merging of same xact ID puts/gets
2016-07-05 12:08:22 -07:00
51f7bf1511
fix Bufferless voluntary release issue
2016-07-05 12:08:22 -07:00
afc51c4a35
make sure TL -> NASTI converter handles multibeat transactions properly
2016-07-05 12:08:22 -07:00
ebefe57036
simplify BTB fetchWidth=1 special case
2016-07-04 23:43:47 -07:00
85808f8cbb
Clean up PseudoLRU code
2016-07-02 15:09:12 -07:00
2d325df60c
Improve PTW simulation performance
2016-07-02 14:34:18 -07:00
5aa8ef1855
Remove invalidation support from BTB
...
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
2016-07-02 14:27:29 -07:00
663002ec0c
Improve TLB simulation performance
2016-07-02 14:26:05 -07:00
af51b6f363
bump groundtest and uncore
2016-07-01 18:13:46 -07:00
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
caa9ca24b9
NASTI -> TL converter also uses ID mapper
2016-07-01 18:11:29 -07:00
39bee5198d
Nasti Puts: decode wmask to determine addr_byte() and op_size()
...
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
2016-07-01 16:49:32 -07:00
e163a23583
fix another bug in Widener
2016-07-01 16:24:48 -07:00
10a46a36ae
fix full_addr() function in TileLink
2016-07-01 15:17:41 -07:00
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
61e3e5b45a
more WIP on fixing Bufferless
2016-06-30 18:29:51 -07:00
0eedffa82f
WIP: Fix BufferlessBroadcastHub
2016-06-30 18:29:51 -07:00
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
ce46f523c9
make sure Widener uses proper parameters to generate acquire/grant
2016-06-30 18:17:16 -07:00
a0b1772404
change TileLinkWidthAdapter interface
2016-06-30 15:50:23 -07:00
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
9feca99d5d
make PutBlock wmask argument match Put
2016-06-28 13:10:46 -07:00
b936aa9826
refactor uncore files into separate packages
2016-06-28 13:10:46 -07:00
c10691b616
Don't take interrupts on instructions in branch shadow
...
In situations like
j 1f
nop
1: nop
the interrupt could be taken on the first nop.
2016-06-28 12:47:49 -07:00
a70dee17ea
Make RoCC energy-saving logic mirror same for D$
2016-06-28 12:47:45 -07:00
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
97e74aec3a
Merge RTC and PRCI
2016-06-27 23:06:07 -07:00
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
ec5b9dfc86
make sure trackers can handle case where there are no caching clients
2016-06-27 16:29:51 -07:00
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
a93a70c8ec
make sure merged voluntary releases are handled properly
2016-06-27 11:40:32 -07:00
800e62412a
use the fast version of asm/bmark-tests
2016-06-24 15:36:10 -07:00
d6ba0437ff
merge different configs into regression suites to reduce travis build times
2016-06-24 13:02:29 -07:00
87a4858aa6
Exit from testbench, not C code
...
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
4cd709c516
fix Comparator in groundtest
2016-06-23 15:47:24 -07:00
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
354b81c8fe
Remove legacy HTIF things
...
The SCR file is gone, too, because it is tightly coupled. The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
2016-06-23 13:17:11 -07:00
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
f57524e0c1
Remove FENCE.I from debug ROM; specialize for RV64
2016-06-23 00:01:26 -07:00
6d43c0a945
Mask interrupts during single-step
2016-06-23 00:01:06 -07:00
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
