82681179cb
[tilelink2] Edges: add size to addr_lo.
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addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
2016-09-12 16:58:09 -07:00
88440ebf89
Use PseudoLRU in BTB when possible (for powers of two)
2016-09-12 16:52:03 -07:00
266a2f24bd
Disable Mul early out by default if XLen == 32
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With a default unroll of 8, it doesn't help performance, but costs area.
2016-09-12 16:50:08 -07:00
96185e4b16
tighten an assert condition
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dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
2016-09-12 16:49:46 -07:00
beb141a20b
Allow M, A, D, C extensions to be disabled in misa register
2016-09-12 16:49:46 -07:00
e66abb5e92
Merge pull request #276 from ucb-bar/nmemchannels-fix
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Pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 14:05:50 -07:00
f3cdeb08c6
pass nMemChannels to coreplex through CoreplexConfig
2016-09-12 12:40:10 -07:00
9d9f90646d
allow configuration of simulation memory latency
2016-09-12 12:33:50 -07:00
49bba961cf
Merge pull request #259 from ucb-bar/refactor-periphery
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Refactor Periphery
2016-09-12 12:18:00 -07:00
a21b04a7c1
playground for making different DAGs to use as DUTs
2016-09-12 10:32:45 -07:00
0671d5d637
Initial version of fuzzer and simple ram fuzz test
2016-09-12 10:32:45 -07:00
7760459b76
tilelink2 RegisterRouter: add RegField test patterns
2016-09-12 10:32:25 -07:00
85ae77c108
tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible
2016-09-12 10:32:25 -07:00
9560df537c
tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests
2016-09-12 10:32:24 -07:00
26f9e2dfbd
tilelink2 Parameters: fix width=1 address truncation bug
2016-09-12 10:32:24 -07:00
98a4facac7
tilelink2 RAMModel: clear Mems on power-up
2016-09-12 10:32:24 -07:00
17f7ab18de
tilelink2 RAMModel: model the state a RAM would have for Put+Gets
2016-09-12 10:32:24 -07:00
488b93d146
tilelink2 Parameters: if you support PutPartial, you must support PutFull
2016-09-12 10:32:24 -07:00
d6261e8ce8
tilelink2 Edge: add a numBeats1 method for predecremented code
2016-09-12 10:32:24 -07:00
5604049927
tilelink2 Buffer: support an unlimited number of channels
2016-09-12 10:32:24 -07:00
d985cdfc66
Merge branch 'master' into refactor-periphery
2016-09-10 23:42:13 -07:00
fea31c7061
let GlobalAddrMap and ConfigString overridable
2016-09-10 23:39:44 -07:00
bb3f514e8d
now able to add periphery devices through traits
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Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
395bc16da6
Merge pull request #271 from ucb-bar/black_box_regs_fix
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Get rid of the unecessary Parameters for Async Reset Reg
2016-09-10 14:14:12 -07:00
77e4aa63f8
Get rid of the unecessary Parameters for Async Reset Reg
2016-09-09 16:24:35 -07:00
e6889ea711
Merge pull request #269 from ucb-bar/tweaks
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Two tweaks to Rocket perf & QoR
2016-09-09 15:25:15 -07:00
b695ab5292
Merge branch 'master' into tweaks
2016-09-09 15:04:21 -07:00
8273ca1ae7
Merge pull request #265 from ucb-bar/black_box_regs
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Make it possible to have Async Reset Flops
2016-09-09 13:54:04 -07:00
5f5989848c
Merge remote-tracking branch 'origin/master' into black_box_regs
2016-09-09 13:12:52 -07:00
cf3c6fa277
add STOP_COND to emulator & match vsim PRINTF_COND
2016-09-09 11:07:17 -07:00
656aa78f7d
Pipeline FMAs more deeply by default
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Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
eaa4b04ee5
Check D$ store->load collisions more precisely
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Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
c4593d2034
Merge pull request #266 from ucb-bar/multinode
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TL2Node: make it possible for {Identity,Output,Input}Node to pass a Vec
2016-09-09 10:17:45 -07:00
c28ca37944
tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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We can more reliably find the current LazyModule from the LazyModule.stack
2016-09-08 23:06:59 -07:00
b587a409a3
tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
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In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
2016-09-08 21:34:20 -07:00
176f385b1d
Merge pull request #263 from ucb-bar/intbar
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TL2 Interrupts
2016-09-08 21:33:25 -07:00
48ca478578
Merge branch 'master' into intbar
2016-09-08 21:09:59 -07:00
808a7f60f4
tilelink2 Legacy: it's only an error if it's valid ( #264 )
2016-09-08 21:09:40 -07:00
fda4c2bd76
Add a way to create Async Reset Registers and a way to easily access them with TL2
2016-09-08 20:02:07 -07:00
c1eb1f12a2
tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices
2016-09-08 20:02:07 -07:00
cbf0670156
tilelink2 Legacy: it's only an error if it's valid
2016-09-08 19:32:00 -07:00
1b07d53f70
tilelink2 IntNodes: record interrupt ranges in parameters
2016-09-08 18:51:43 -07:00
9015276958
Use sbt-launch.jar 0.13.12. ( #262 )
2016-09-08 17:26:04 -07:00
66f58cf2d0
tilelink2 RegisterRouter: support new TL2 interrupts
2016-09-08 15:25:50 -07:00
23e896ed5d
tilelink2 IntNodes: support interrupt graphs
2016-09-08 15:25:48 -07:00
d7df7d3109
tilelink2: connect Nodes to LazyModules for better error messages
2016-09-08 15:24:04 -07:00
53987cd9d4
tilelink2 Nodes: support non-Bundle data for io type
2016-09-08 15:19:12 -07:00
a44fff5d93
Merge pull request #260 from ucb-bar/w1ToClear
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W1 to clear
2016-09-08 14:27:03 -07:00
60a503dc2f
tilelink2 RegField: add a w1ToClear RegField
2016-09-08 14:02:49 -07:00
99b7e734cd
tilelink2 Bundles: fix wrong sink width!
2016-09-08 13:47:40 -07:00
Henry Cook
Andrew Waterman
Andrew Waterman
Howard Mao
Wesley W. Terpstra
Yunsup Lee
mwachs5
Colin Schmidt
Henry Cook
Yunsup Lee
Richard Xia