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3429 Commits

Author SHA1 Message Date
Wesley W. Terpstra 9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Yunsup Lee 2c000a99da compartmentalize Top into periphery traits 2016-09-08 02:08:57 -07:00
Yunsup Lee 8536a2a47d Merge pull request #257 from ucb-bar/fix-non-contiguous-mmio-region-routing 
Fix routing in non-contiguous MMIO regions
 2016-09-08 00:03:11 -07:00
Howard Mao 62e33527d3 Merge branch 'master' into fix-non-contiguous-mmio-region-routing 2016-09-07 23:35:12 -07:00
Howard Mao 4592558047 Merge pull request #254 from ucb-bar/inferRW 
Turn on the inferRW Firrtl pass
 2016-09-07 21:59:05 -07:00
Yunsup Lee e35e7b2ee3 Fix routing in non-contiguous MMIO regions 
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
 2016-09-07 19:28:12 -07:00
Ben Keller 6be569be9f Turn on the inferRW Firrtl pass 
Without this, all of the memories wind up as two-ported.
 2016-09-07 15:27:26 -07:00
Howard Mao 7a6f155b2a Merge pull request #253 from ucb-bar/use-companion 
only use companion objects for types
 2016-09-07 15:07:17 -07:00
Andrew Waterman 7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Andrew Waterman 58c87bdf32 Merge pull request #245 from ucb-bar/tilelink2.2 
Tilelink2
 2016-09-07 12:56:22 -07:00
Colin Schmidt 254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
Andrew Waterman 23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
Andrew Waterman 02a2439222 Support a degenerate PLIC with no interrupts 
Resolves #249
 2016-09-07 11:21:13 -07:00
Colin Schmidt 92718e4b61 fix null statement in vsli_mem_gen ala firrtl#264 (#252) 2016-09-07 11:04:36 -07:00
Andrew Waterman 70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC 
The latter is more the domain of TinyConfig.
 2016-09-07 01:58:25 -07:00
Andrew Waterman a7f47f3c23 Reduce default BTB size 
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
 2016-09-07 01:51:27 -07:00
Andrew Waterman 9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman 66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman 511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Yunsup Lee fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
 2016-09-07 00:05:00 -07:00
Wesley W. Terpstra d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Yunsup Lee b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) 
now you can add them in any order.  there's an explicit check at the end to figure out whether there are overlapping regions.
 2016-09-06 21:53:55 -07:00
Howard Mao 7504498dff Merge pull request #247 from ucb-bar/replseqmem_pr 
Bump FIRRTL for Sequential Memories
 2016-09-06 17:22:18 -07:00
Megan Wachs e95fe646a3 mem_gen failure doesn't create the target 2016-09-06 16:29:29 -07:00
Howard Mao bbef3a8d3e Merge pull request #246 from ucb-bar/fix-configstring-printout-problem 
fix configstring printout with no memory
 2016-09-06 15:31:39 -07:00
Megan Wachs 48098f5e2d Bump FIRRTL to instantiate Sequential Memory Macros 2016-09-06 14:48:28 -07:00
Megan Wachs 1fec9807f6 allow override of vlsi_mem_gen script 2016-09-06 14:44:12 -07:00
Wesley W. Terpstra aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Yunsup Lee 56d81b0034 fix configstring printout with no memory 2016-09-06 10:40:11 -07:00
Wesley W. Terpstra 54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra 314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra 56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra 3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00