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Author SHA1 Message Date
Henry CookandGitHub 5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire 
Halt and Catch Fire
 2017-09-22 09:30:30 -07:00
Henry Cook 81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook 28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Henry CookandGitHub 323a207bdd Merge pull request #1005 from freechipsproject/trace 
Rename trace.addr -> iaddr
 2017-09-20 15:34:45 -07:00
Henry CookandGitHub 1cb91eed41 Merge pull request #1003 from freechipsproject/ma-fetch 
Don't write badaddr on misaligned fetch exceptions
 2017-09-20 14:28:26 -07:00
Henry CookandGitHub 00cf089350 Merge pull request #1002 from freechipsproject/trace 
Add instruction-trace port
 2017-09-20 11:50:40 -07:00
Henry CookandGitHub 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Henry CookandGitHub 9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Henry CookandGitHub e8702e2687 Merge pull request #989 from freechipsproject/config-cleanups 
Clean up various Configs/Fields/Params
 2017-09-15 13:45:15 -07:00
Henry Cook e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook 56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook 37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry CookandGitHub 063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Henry Cook 9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook 3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Henry CookandWesley W. Terpstra a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Henry Cook 32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Henry CookandGitHub c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer 
tilelink: allow insertion of TLDelayer on TLBus outward node
 2017-08-07 19:01:39 -07:00
Henry Cook c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
Henry Cook 2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Henry Cook c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Henry Cook 11332c1226 dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative 2017-07-31 14:03:30 -07:00
Henry CookandGitHub 7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup 
Stabilize tile wrappers for downstream tools
 2017-07-28 10:52:59 -07:00
Henry Cook b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook 289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 2017-07-27 15:44:51 -07:00
Henry Cook 266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Henry Cook 9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook 33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Henry CookandYunsup Lee 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Henry CookandGitHub 4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Henry CookandWesley W. Terpstra 6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Henry CookandWesley W. Terpstra ad4b454b49 isp: passthru based on edgesOut = edgesIn (#814) 2017-06-22 21:23:49 -07:00
Henry CookandGitHub 0fdaa28694 Merge pull request #811 from freechipsproject/isp-tweaks 
Assorted changes based on ISP use cases
 2017-06-20 19:24:28 -07:00
Henry Cook bf431c0a53 groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
Henry Cook 1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names 2017-06-20 17:18:45 -07:00
Henry Cook 5552f23294 tims: explictly name them for generated address map 2017-06-20 17:18:29 -07:00
Henry Cook 6b79842e66 dcache: just left shift by untagbits to get tag 
Always safe because of the requirement on coreplex/RocketTiles.scala:126
 2017-06-20 16:35:28 -07:00
Henry CookandGitHub 7521050a48 Merge pull request #810 from freechipsproject/isp-fixes 
ISP fixes
 2017-06-20 16:35:06 -07:00
Henry CookandGitHub 5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Henry CookandGitHub 8278d22fcd Merge pull request #776 from freechipsproject/lazy-raw-module-imp 
Use LazyMultiIOModuleImp to simplify top-level traits
 2017-06-13 15:50:12 -07:00
Henry Cook 80a3278139 travis: travis_wait to 80 2017-06-13 14:24:40 -07:00
Henry Cook 9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook 2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Henry CookandGitHub 940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Henry CookandGitHub 991a67ac68 Merge pull request #749 from freechipsproject/unit-test-speedup 
Unit test speedup
 2017-05-17 16:28:42 -07:00
Henry CookandGitHub 733ebbce0e Update README.md (#748) 2017-05-17 14:53:56 -07:00
Henry CookandGitHub dfabf68d9c Merge pull request #746 from freechipsproject/fix-bundle-refs 
diplomacy: provide connect access to edges without bundles
 2017-05-17 12:28:46 -07:00
Henry Cook 5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00
Henry Cook a19fc2549e tile: add tileBus xbar 2017-05-16 16:12:01 -07:00
Henry Cook 5f3a4ada1b diplomacy: add legalize method to AddressSet 2017-05-10 12:54:24 -07:00
Henry Cook 3af40bff8b tilelink: better address masking for fuzzing 2017-05-10 12:54:24 -07:00
Henry CookandGitHub 7b3d87a2e6 Merge pull request #723 from ucb-bar/fuzz-ranges 
Allow TL fuzzing range to be overridden
 2017-05-03 16:30:10 -07:00
Henry Cook 1f1240baf1 fuzzer: allow fuzzing range to be overridden 2017-05-03 15:29:14 -07:00
Henry CookandGitHub cd547fabbd Merge pull request #695 from ucb-bar/pipeline-mmio 
Pipeline AXI4 MMIO
 2017-05-03 11:25:24 -07:00
Henry CookandGitHub 05ca88fb47 Merge branch 'master' into pipeline-mmio 2017-05-03 01:59:59 -07:00
Henry CookandGitHub 4dd3345db2 Merge branch 'master' into pipeline-mmio 2017-05-02 16:23:26 -07:00
Henry CookandAndrew Waterman 3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Henry CookandAndrew Waterman bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex 2017-04-27 18:17:09 -07:00
Henry Cook e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Henry CookandGitHub 635f119422 Merge pull request #709 from ucb-bar/bump-hardfloat 
bump hardfloat
 2017-04-26 16:47:49 -07:00
Henry Cook ebe27614d2 bump hardfloat 2017-04-26 15:37:29 -07:00
Henry CookandGitHub 0a9f632cb0 Merge pull request #708 from ucb-bar/debug_busy_data 
debug: Prevent writes to DATA/PROGBUF when busy
 2017-04-26 14:32:10 -07:00
Henry CookandGitHub 1bdb247002 Merge pull request #697 from ucb-bar/async_queue_option 
Add narrowData option to AsyncQueue.
 2017-04-25 17:43:28 -07:00
Henry CookandGitHub 7f5f1c7631 Merge branch 'master' into async_queue_option 2017-04-25 14:58:11 -07:00
Henry CookandGitHub 95591cc608 Merge pull request #704 from ucb-bar/verbose-require 
Miscellaneous uncore cleanups
 2017-04-25 14:57:58 -07:00
Henry CookandGitHub 9bb0d92381 Merge branch 'master' into async_queue_option 2017-04-25 11:23:22 -07:00
Henry Cook 60d71efa36 ahb: make hreadyout fuzzing a sram parameter 2017-04-25 11:11:31 -07:00
Henry Cook ca435c2f40 uncore: more verbose requires 2017-04-25 11:11:31 -07:00
Henry CookandWesley W. Terpstra 54820e094d Make more require statements in diplomacy verbose (#693) 
* diplomacy: add more verbose requirements
* bump firrtl
 2017-04-20 13:18:39 -07:00
Henry CookandWesley W. Terpstra ef8a819763 Miscellaneous periphery improvements (#689) 
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
 2017-04-20 11:28:00 -07:00
Henry CookandGitHub 9f371abf3b Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10 
Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v0…
 2017-03-31 01:56:36 -07:00
Henry CookandGitHub e92eaa7156 Merge branch 'master' into riscv-tools-on-priv-1.10 2017-03-30 22:31:29 -07:00
Henry CookandGitHub e8f337e963 Merge pull request #636 from ucb-bar/name-rams 
Name L1$ RAMs consistently
 2017-03-30 22:30:12 -07:00
Henry CookandGitHub b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Henry CookandGitHub b6da81a66c Merge pull request #624 from ucb-bar/debug_v013_pr 
Debug v013 [WIP]
 2017-03-30 17:35:26 -07:00
Henry CookandGitHub bcaee9834c travis_wait 30 2017-03-30 13:22:33 -07:00
Henry CookandAndrew Waterman d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
Henry CookandWesley W. Terpstra 996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Henry CookandGitHub 797c18b8db Make some requirement failures more verbose (#608) 
* tilelink: verbose requires in xbar

* diplomacy: verbose requires
 2017-03-23 21:55:11 -07:00
Henry CookandGitHub 055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) 2017-03-22 14:38:33 -07:00
Henry CookandGitHub 4f5f686c7e bump riscv-tools (#586) 2017-03-15 18:09:26 -07:00
Henry CookandGitHub e9c694522b Merge pull request #578 from ucb-bar/priv-1.10 
Privileged architecture updates
 2017-03-14 13:20:19 -07:00
Henry CookandGitHub bb0390630c Merge branch 'master' into priv-1.10 2017-03-13 21:40:12 -07:00
Henry CookandGitHub 4eb261c895 Merge pull request #582 from ucb-bar/more-fuzzing 
Fuzzer enhancements
 2017-03-13 15:31:51 -07:00
Henry Cook fe287864ef bump firrtl 2017-03-13 13:14:16 -07:00
Henry CookandGitHub 1a3fec61c0 Merge branch 'master' into priv-1.10 2017-03-13 11:59:18 -07:00
Henry CookandAndrew Waterman dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Henry CookandWesley W. Terpstra 4af437fdab RANDOMIZE_MEM_INIT vlsi_mem_gen (#572) 2017-03-07 01:56:15 -08:00
Henry CookandGitHub d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry CookandGitHub 229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Henry CookandGitHub 33ffb62326 Merge pull request #568 from ucb-bar/elide-empty-int-ext 
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
 2017-03-03 12:46:11 -08:00