Howard Mao
338f959620
get rid of commented out code
2016-06-22 17:36:53 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Palmer Dabbelt
cddfdf0929
Add CHISEL_VERSION make argument
...
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
db9de94588
Generate and use SCR address header files
...
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Palmer Dabbelt
00465b15c3
Allow the regression Makefile to clean all targets
2016-01-31 23:06:59 -08:00
Andrew Waterman
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
Yunsup Lee
1e772daeea
no spaces in Makefrag
2015-11-05 16:42:05 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
Yunsup Lee
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Yunsup Lee
d6df479870
move 'include /Makefrag' out of top-level Makefrag
2015-07-14 16:13:32 -07:00
Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
...
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Schuyler Eldridge
a42832fc70
Fix fpga_mem_gen for Python 2 and 3 Environments
...
Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00
Yunsup Lee
70b0f9fd4d
error out for PCWM-L, port width mismatch
2014-09-25 06:50:50 -07:00
Scott Beamer
1a101f8de5
don't use latches on mem ports for fpga
2014-09-25 06:46:21 -07:00
Yunsup Lee
221007595b
allow BACKEND/CONFIG be environment variables
2014-09-17 11:12:08 -07:00
Yunsup Lee
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
Yunsup Lee
275b72368b
add CONFIG to the name of simulator executable
2014-09-11 22:11:58 -07:00
Yunsup Lee
02c08a156f
generate consts.vh from chisel source
2014-09-10 17:14:55 -07:00
Yunsup Lee
ddfd3ce968
further generalize fpga/vlsi builds
2014-09-08 00:21:57 -07:00
Yunsup Lee
1cb2d1d7b7
initialize all SRAMs to avoid X propagation problem
2014-09-04 11:06:01 -07:00
Yunsup Lee
763c57931b
fix problem introduced with verilog generation in vsim/fsim
2014-09-04 09:49:57 -07:00
Scott Beamer
6c6f5a3843
add verilog target to build without simulator
2014-09-03 17:28:45 -07:00
Yunsup Lee
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
