add Zscale testing

fsim/Makefile

@@ -17,6 +17,7 @@ output_dir = $(sim_dir)/output
 
 BACKEND ?= fpga
 CONFIG ?= DefaultFPGAConfig
+TB ?= rocketTestHarness
 
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag

fsim/Makefrag

@@ -9,7 +9,7 @@ sim_vsrcs = \
 	$(generated_dir)/$(MODEL).$(CONFIG).v \
 	$(generated_dir)/consts.$(CONFIG).vh \
 	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
-	$(base_dir)/vsrc/rocketTestHarness.v \
+	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/backup_mem.v \
 
 # C sources
@@ -45,7 +45,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(sim_dir)/libdramsim.a \
 	+define+FPGA \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND=rocketTestHarness.verbose \
+	+define+PRINTF_COND=$(TB).verbose \
 	+libext+.v \
 
 #--------------------------------------------------------------------