riscv/rocket-chip
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Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used

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Henry Cook committed 2015-07-28 00:24:07 -07:00
1 parent efd6458a3d
commit d21ffa4dba
7 files changed
+32 -29
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fsim/Makefile
+2 -2
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@@ -21,8 +21,8 @@ TB ?= rocketTestHarness
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
-include $(generated_dir)/Makefrag-tests.$(CONFIG)
include $(base_dir)/vsim/Makefrag-sim
-include $(generated_dir)/$(MODEL).$(CONFIG).d
include $(base_dir)/vsim/Makefrag-verilog
all: $(simv)
debug: $(simv_debug)