update for rocket-chip release
This commit is contained in:
Yunsup Lee
18
fsim/.gitignore
vendored
Normal file
18
fsim/.gitignore
vendored
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@ -0,0 +1,18 @@
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simv*
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csrc
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*.vpd
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*.key
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DVE*
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.vcs*
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timestamp
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*.out
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*.h
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*.log
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*.cmd
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*.daidir
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*.ucli
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*.a
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*.vcd
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dramsim2_ini
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generated-src
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output
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25
fsim/Makefile
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25
fsim/Makefile
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#=======================================================================
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# Makefile for Verilog simulation w/ VCS
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#-----------------------------------------------------------------------
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# Yunsup Lee (yunsup@cs.berkeley.edu)
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#
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# This makefile will build a rtl simulator and run various tests to
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# verify proper functionality.
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#
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default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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mem_gen = $(base_dir)/fsim/fpga_mem_gen
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sim_dir = .
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output_dir = $(sim_dir)/output
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include $(base_dir)/Makefrag
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include $(sim_dir)/Makefrag
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include $(base_dir)/vsim/Makefrag-sim
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all: $(simv)
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clean:
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rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
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68
fsim/Makefrag
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68
fsim/Makefrag
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#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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sim_vsrcs = \
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$(generated_dir)/$(FPGAMODEL).v \
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$(generated_dir)/$(FPGAMODEL)Mem.v \
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$(generated_dir)/memdessertMemDessert.v \
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$(base_dir)/vsrc/const.vh \
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$(base_dir)/vsrc/rocketTestHarness.v \
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$(base_dir)/vsrc/bram_mem.v \
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/vcs_main.cc \
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$(base_dir)/csrc/mm.cc \
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$(base_dir)/csrc/mm_dramsim2.cc \
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-I$(realpath $(base_dir))/dramsim2" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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+define+FPGA \
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+define+TOP=$(FPGAMODEL) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=rocketTestHarness.verbose \
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+libext+.v \
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
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cd $(sim_dir) && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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simv_debug = $(sim_dir)/simv-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
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cd $(sim_dir) && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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# +define+MEM_BACKUP_EN \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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185
fsim/fpga_mem_gen
Executable file
185
fsim/fpga_mem_gen
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@ -0,0 +1,185 @@
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#!/usr/bin/env python
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import sys
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import math
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# This is based off of reference-chip/vlsi/src/vlsi_mem_gen
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use_latches = 1
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module_template = '''module %s(
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%s
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);
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%s
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%s
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always @(posedge CLK) begin
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%s
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end
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%s
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endmodule
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'''
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mask_assert_template = '''
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`ifndef SYNTHESIS
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integer i;
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integer j;
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always @(posedge CLK) begin%s
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end
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`endif
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'''
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assert_template = '''
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for (i=0; i<%d; i=i+%d) begin
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for (j=1; j<%d; j=j+1) begin
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if (%sM[i] != %sM[i+j]) begin
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$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\\n");
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$finish;
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end
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end
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end'''
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def parse_line(line):
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name = ''
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width = 0
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depth = 0
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ports = ''
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mask_gran = 1
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tokens = line.split()
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i = 0
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for i in xrange(0,len(tokens),2):
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s = tokens[i]
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if s == 'name':
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name = tokens[i+1]
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elif s == 'width':
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width = int(tokens[i+1])
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elif s == 'depth':
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depth = int(tokens[i+1])
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elif s == 'ports':
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ports = tokens[i+1].split(',')
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elif s == 'mask_gran':
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mask_gran = int(tokens[i+1])
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else:
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sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
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return (name, width, depth, ports, mask_gran)
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def gen_range(mask_index, mask_gran, max_width):
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return '%d:%d' % (min(mask_gran*(mask_index+1),max_width)-1,
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min(mask_gran*(mask_index),max_width))
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def gen_mem(name, width, depth, ports, mask_gran):
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addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
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mask_width = int(math.ceil(float(width) / mask_gran))
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port_spec = ['input CLK', 'input RST', 'input init']
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readports = []
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writeports = []
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latchports = []
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rwports = []
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decl = []
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combinational = []
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sequential = []
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maskedports = {}
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mask_asserts = ''
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for pid in range(len(ports)):
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ptype = ports[pid]
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if ptype[0:1] == 'm':
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ptype = ptype[1:]
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maskedports[pid] = pid
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if ptype == 'read':
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port_spec += ['input [%d:0] R%dA' % (addr_width-1, pid)]
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port_spec += ['input R%dE' % pid]
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port_spec += ['output [%d:0] R%dO' % (width-1, pid)]
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readports += [pid]
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elif ptype == 'write':
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port_spec += ['input [%d:0] W%dA' % (addr_width-1, pid)]
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port_spec += ['input W%dE' % pid]
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port_spec += ['input [%d:0] W%dI' % (width-1, pid)]
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if pid in maskedports:
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port_spec += ['input [%d:0] W%dM' % (width-1, pid)]
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if not use_latches or pid in maskedports:
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writeports += [pid]
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else:
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latchports += [pid]
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elif ptype == 'rw':
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port_spec += ['input [%d:0] RW%dA' % (addr_width-1, pid)]
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port_spec += ['input RW%dE' % pid]
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port_spec += ['input RW%dW' % pid]
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if pid in maskedports:
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port_spec += ['input [%d:0] RW%dM' % (width-1, pid)]
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port_spec += ['input [%d:0] RW%dI' % (width-1, pid)]
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port_spec += ['output [%d:0] RW%dO' % (width-1, pid)]
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rwports += [pid]
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else:
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sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
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decl += ['reg [%d:0] ram [%d:0];' % (width-1, depth-1)]
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for pid in readports:
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decl += ['reg [%d:0] reg_R%dA;' % (addr_width-1, pid)]
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sequential += ['if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid)]
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combinational += ['assign R%dO = ram[reg_R%dA];' % (pid, pid)]
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for pid in rwports:
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decl += ['reg [%d:0] reg_RW%dA;' % (addr_width-1, pid)]
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sequential += ['if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid)]
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combinational += ['assign RW%dO = ram[reg_RW%dA];' % (pid, pid)]
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for pid in latchports:
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decl += ['reg [%d:0] latch_W%dA;' % (addr_width-1, pid)]
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decl += ['reg [%d:0] latch_W%dI;' % (width-1, pid)]
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decl += ['reg latch_W%dE;' % (pid)]
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combinational += ['always @(*) begin']
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combinational += [' if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid)]
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combinational += [' if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid)]
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combinational += [' if (!CLK) latch_W%dE <= W%dE;' % (pid, pid)]
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combinational += ['end']
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combinational += ['always @(*)']
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combinational += [' if (CLK && latch_W%dE)' % (pid)]
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combinational += [' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid)]
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for pid in writeports:
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if pid not in maskedports:
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sequential += ['if (W%dE) ram[W%dA] <= W%dI;' % (pid, pid, pid)]
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else:
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for mask_index in range(mask_width):
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rs = gen_range(mask_index, mask_gran, width)
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sequential += ['if (W%dE && W%dM[%d]) ram[W%dA][%s] <= W%dI[%s];' %
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(pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
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mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'W'+str(pid), 'W'+str(pid))
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for pid in rwports:
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if pid not in maskedports:
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sequential += ['if (RW%dE && RW%dW) ram[RW%dA] <= RW%dI;' % (pid, pid, pid, pid)]
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else:
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for mask_index in range(mask_width):
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rs = gen_range(mask_index, mask_gran, width)
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sequential += ['if (RW%dE && RW%dW && RW%dM[%d]) ram[RW%dA][%s] <= RW%dI[%s];' %
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(pid, pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
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mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'RW'+str(pid), 'RW'+str(pid))
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check_masks = '' if len(maskedports) == 0 else mask_assert_template % mask_asserts
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return module_template % (name,
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',\n '.join(port_spec),
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check_masks,
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'\n '.join(decl),
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'\n '.join(sequential),
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'\n '.join(combinational))
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def main():
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if len(sys.argv) < 2:
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sys.exit('Please give a .conf file as input')
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for line in open(sys.argv[1]):
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print gen_mem(*parse_line(line))
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if __name__ == '__main__':
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main()
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