riscv
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rocket-chip
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320 Commits

Author SHA1 Message Date
Henry Cook 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
 2013-08-15 16:39:30 -07:00
Henry Cook 784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook 9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Huy Vo d7d13255db chisel tag 2013-08-12 20:53:29 -07:00
Huy Vo f9d1403a92 tags 2013-08-12 20:53:17 -07:00
Huy Vo cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Henry Cook 11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook 199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00
Stephen Twigg c1b1a21a0f If +stats is set when running simv-debug, will only output vcd data when cr28 is high. 2013-07-30 16:39:47 -07:00
Henry Cook 4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
Stephen Twigg 3f874342a4 Update chisel to appropriate version for reference chip build. 2013-07-10 17:08:56 -07:00
Ben Keller c7bf1aaac9 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-07-10 16:01:25 -07:00
Ben Keller a72e0dc99e Updated riscv-tools reference 2013-07-10 16:01:01 -07:00
Henry Cook 2796de01bf new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:41:27 -07:00
Andrew Waterman c5f01f3f87 update rocket 2013-06-15 00:55:34 -07:00
Andrew Waterman 4ae0c68303 require -std=c++11, as -std=c++0x doesn't cut it 2013-06-14 00:28:42 -07:00
Henry Cook 896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook 85fbb650c9 makefile support for new multithreading tests 2013-06-13 15:34:54 -07:00
Andrew Waterman ae0716fb6d Use chisel printf for logging 2013-06-13 10:53:23 -07:00
Stephen Twigg bd43ca8423 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-05-23 17:51:24 -07:00
Henry Cook c06cbf523b Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
Henry Cook 6a69d7d7b5 pass closure to generate bank addr 2013-05-23 14:58:19 -07:00
Yunsup Lee 26ed805862 push chisel,riscv-rocket,uncore 
linux kernel boots!
 2013-05-21 19:00:40 -07:00
Yunsup Lee f3c78abc2b push riscv-tests 2013-05-16 00:51:02 -07:00
Yunsup Lee e77bde71d0 push riscv-tools 2013-05-15 12:03:52 -07:00
Yunsup Lee f0b0867f5a push riscv-tests 2013-05-13 19:22:28 -07:00
Yunsup Lee f13605d2f5 push riscv-tools 2013-05-13 19:14:57 -07:00
Yunsup Lee 7ba3ab03e2 update README 2013-05-13 11:19:55 -07:00
Yunsup Lee 5b55cc93af add submodule riscv-tools 2013-05-10 11:53:55 -07:00
Andrew Waterman e8fcdb56a6 update chisel to work around xilinx ise bug 2013-05-03 01:47:15 -07:00
Andrew Waterman d825c9d6e9 make fpga Makefile work with updated Makefrag 2013-05-02 05:09:45 -07:00
Andrew Waterman cfa86dba4f add FPGA test bench 
The memory models now support back pressure on the response.
 2013-05-02 04:59:32 -07:00
Andrew Waterman d2e1828714 gracefully kill htif thread, fixing tty stuff 2013-05-02 04:59:32 -07:00
Yunsup Lee a86ad08c1e commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
Andrew Waterman 50bd9a08a7 resynchronize fpga uncore 2013-05-01 01:12:47 -07:00
Yunsup Lee a2f584e928 add riscv-tests, get rid of riscv-asmtests-bmarks 2013-04-29 19:29:51 -07:00
Yunsup Lee 7fe052e1bf update README 2013-04-24 02:05:28 -07:00
Yunsup Lee 9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
Yunsup Lee 93df795e48 change LLC leaf SRAM size 2013-04-22 11:06:50 -07:00
Andrew Waterman 7f5282d355 replace RDNPC with AUIPC 2013-04-22 04:21:46 -07:00
Huy Vo 2ac3fd5306 get rid of init_node 2013-04-20 01:36:32 -07:00
Huy Vo 0d87e3bacc fixed init pin generation 2013-04-20 00:38:01 -07:00
Henry Cook a01cdf95fd tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps 2013-04-10 13:53:27 -07:00
Henry Cook d7982bf27f bump uncore for grant fix 2013-04-09 14:29:49 -07:00
Andrew Waterman 7ea782fd22 add LR/SC 2013-04-07 19:36:15 -07:00
Henry Cook c6b56c5f25 bump rocket for coherence bug fix 2013-04-04 15:52:20 -07:00
Henry Cook 9d5e97d89e override io in LogicalNetwork 2013-03-28 14:10:20 -07:00
Henry Cook 16ad8a7e9c Fixes after merge 2013-03-25 19:14:38 -07:00
Andrew Waterman 8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook eec590c1bf Added support for multiple L2 banks. Moved tile IO queueing. 2013-03-25 17:01:46 -07:00