b7c0d0cb4d
test both cached and uncached cases in MixedAllocPutRegression
2016-06-14 17:32:29 -07:00
1074c9fe6d
change the way regression IOs are assigned
2016-06-14 11:06:45 -07:00
e284257052
fully disable the cache when not using it in regression tests
2016-06-14 11:06:45 -07:00
3e105eb352
make sure MixedAllocPutRegression uses a block that hasn't been cached already
2016-06-13 18:17:48 -07:00
fe8d81958f
fix groundtests to fit new way of parameterizing TileLink clients
2016-06-13 16:17:27 -07:00
a921458758
add a regression test for no-alloc Put following an alloc Put
2016-06-13 16:17:27 -07:00
4b4e8f7f62
fixes for priv-1.9 changes
2016-05-02 18:25:02 -07:00
5e793427eb
use address map instead of MMIOBase
2016-04-21 15:38:43 -07:00
d5153bf42e
don't connect unnecessary wires in regression test
2016-04-12 15:38:55 -07:00
55df7d97cc
add regression test for put immediately before put block
2016-04-12 15:38:55 -07:00
7285f5e6bf
Don't drive D$ kill/phys signals for SimpleHellaCacheIF
...
They don't do anything.
2016-04-01 19:31:54 -07:00
af3bc1cb79
don't use ROM for partial writemask regression
2016-03-25 14:06:06 -07:00
5372f181b1
add in missing connections for regression test
2016-03-25 14:05:52 -07:00
471f4c2695
change WriteMaskedPutBlockRegression for better bug detection
...
Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
2016-03-23 16:31:19 -07:00
da302504a5
get rid of sequential same id get regression in broadcast regression suite
2016-02-19 23:14:34 -08:00
24eecee148
add DMA test
2015-12-16 21:26:22 -08:00
4858ca9a60
add a regression to test proper writeback
2015-12-16 21:05:56 -08:00
176d3c890c
add some more regression tests
2015-12-15 23:00:17 -08:00
484e8ce20b
add regression tests for catching specific memory bugs
2015-12-06 02:57:45 -08:00
