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Commit Graph

81 Commits

Author SHA1 Message Date
Richard Xia
183ae58704 Use a random port number for JTAG VPI. 2016-10-26 11:40:45 -07:00
Andrew Waterman
6472d4c245 Print Verilator random seed when +verbose is passed 2016-10-04 22:29:39 -07:00
Andrew Waterman
2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
Henry Cook
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Scott Beamer
cd12fd1cbb fix clang support for emulator-debug 2016-09-14 12:20:37 -07:00
Colin Schmidt
cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00
Andrew Waterman
2dfcf18167 Filter simv command-line args starting with -cm
These confuse HTIF, so don't pass them through.

Contributed by @scottj97.
2016-08-31 13:39:35 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
b64998ec05 make sure dramsim reads and writes occur in the order they are received 2016-07-11 18:11:00 -07:00
Andrew Waterman
9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew Waterman
87a4858aa6 Exit from testbench, not C code
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Andrew Waterman
4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Howard Mao
cf716fea58 fix mm_dramsim2 2016-03-29 20:16:07 -07:00
Palmer Dabbelt
8c73d10fe1 Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
Palmer Dabbelt
a073c37e36 The FPGA doesn't have an HTIF clock divider
We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.
2016-02-22 16:15:07 -08:00
Palmer Dabbelt
926efd0cab Allow the number of memory channels to be picked at runtime
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Howard Mao
6fc1e92708 add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE
Fixes #17
2015-09-24 23:56:41 -04:00
Scott Beamer
fbc6e695d3 remove bugs from float_fix 2015-09-23 16:11:47 -07:00
Scott Beamer
56daea793a allow float_fix to take stdin (for piping) 2015-09-23 16:09:09 -07:00
Howard Mao
38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao
4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Scott Beamer
de81762f7c faster and more conservative float_fix 2015-09-15 17:19:29 -07:00
Scott Beamer
7e25b1ce03 cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
Scott Beamer
3eed7ff238 make float_fix more conservative with replacement 2015-09-12 11:00:00 -07:00
Scott Beamer
a12cd13190 tool to unrecode single floats from commit logs 2015-09-11 20:19:18 -07:00
Christopher Celio
c8a7deb950 Added a commitlog post-processor for Rocket
- Useful for taking Rocket's out-of-order writebacks and generating an
    in-order commit log.
  - Resulting commit log can be diffed against Spike's commit log.
2015-09-11 16:06:01 -07:00