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Get rid of MemIO in Top and replace with AXI throughout

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This commit is contained in:
Howard Mao
2015-10-14 11:33:18 -07:00
parent 032bdd0601
commit 9dabcab9c2
10 changed files with 651 additions and 299 deletions
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46
csrc/emulator.cc
View File

@ -69,10 +69,12 @@ int main(int argc, char** argv)
srand(random_seed);
tile.init(random_seed);
uint64_t mem_width = tile.Top__io_mem_r_bits_data.width() / 8;
// Instantiate and initialize main memory
mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
try {
mm->init(memsz_mb*1024*1024, tile.Top__io_mem_resp_bits_data.width()/8, LINE_SIZE);
mm->init(memsz_mb*1024*1024, mem_width, LINE_SIZE);
}
catch (const std::bad_alloc& e) {
fprintf(stderr,
@ -104,11 +106,19 @@ int main(int argc, char** argv)
while (!htif->done() && trace_count < max_cycles && ret == 0)
{
tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
memcpy(tile.Top__io_mem_resp_bits_data.values, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
tile.Top__io_mem_ar_ready = LIT<1>(mm->ar_ready());
tile.Top__io_mem_aw_ready = LIT<1>(mm->aw_ready());
tile.Top__io_mem_w_ready = LIT<1>(mm->w_ready());
tile.Top__io_mem_b_valid = LIT<1>(mm->b_valid());
tile.Top__io_mem_b_bits_resp = LIT<64>(mm->b_resp());
tile.Top__io_mem_b_bits_id = LIT<64>(mm->b_id());
tile.Top__io_mem_r_valid = LIT<1>(mm->r_valid());
tile.Top__io_mem_r_bits_resp = LIT<64>(mm->r_resp());
tile.Top__io_mem_r_bits_id = LIT<64>(mm->r_id());
tile.Top__io_mem_r_bits_last = LIT<1>(mm->r_last());
memcpy(tile.Top__io_mem_r_bits_data.values, mm->r_data(), mem_width);
try {
tile.clock_lo(LIT<1>(0));
@ -119,15 +129,25 @@ int main(int argc, char** argv)
}
mm->tick(
tile.Top__io_mem_req_cmd_valid.lo_word(),
tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
tile.Top__io_mem_ar_valid.lo_word(),
tile.Top__io_mem_ar_bits_addr.lo_word(),
tile.Top__io_mem_ar_bits_id.lo_word(),
tile.Top__io_mem_ar_bits_size.lo_word(),
tile.Top__io_mem_ar_bits_len.lo_word(),
tile.Top__io_mem_req_data_valid.lo_word(),
tile.Top__io_mem_req_data_bits_data.values,
tile.Top__io_mem_aw_valid.lo_word(),
tile.Top__io_mem_aw_bits_addr.lo_word(),
tile.Top__io_mem_aw_bits_id.lo_word(),
tile.Top__io_mem_aw_bits_size.lo_word(),
tile.Top__io_mem_aw_bits_len.lo_word(),
tile.Top__io_mem_resp_ready.to_bool()
tile.Top__io_mem_w_valid.lo_word(),
tile.Top__io_mem_w_bits_strb.lo_word(),
tile.Top__io_mem_w_bits_data.values,
tile.Top__io_mem_w_bits_last.lo_word(),
tile.Top__io_mem_r_ready.to_bool(),
tile.Top__io_mem_b_ready.to_bool()
);
if (tile.Top__io_host_clk_edge.to_bool())

119
csrc/mm.cc
View File

@ -7,12 +7,38 @@
#include <cstring>
#include <cassert>
void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
{
if (addr > this->size) {
fprintf(stderr, "Invalid write address %lx\n", addr);
exit(EXIT_FAILURE);
}
uint8_t *base = this->data + addr;
for (int i = 0; i < size; i++) {
if (strb & 1)
base[i] = data[i];
strb >>= 1;
}
}
std::vector<char> mm_t::read(uint64_t addr, uint64_t size)
{
if (addr > this->size) {
fprintf(stderr, "Invalid read address %lx\n", addr);
exit(EXIT_FAILURE);
}
uint8_t *base = this->data + addr;
return std::vector<char>(base, base + size);
}
void mm_t::init(size_t sz, int wsz, int lsz)
{
assert(wsz > 0 && lsz > 0 && (lsz & (lsz-1)) == 0 && lsz % wsz == 0);
word_size = wsz;
line_size = lsz;
data = new char[sz];
data = new uint8_t[sz];
size = sz;
}
@ -27,52 +53,67 @@ void mm_magic_t::init(size_t sz, int wsz, int lsz)
dummy_data.resize(word_size);
}
void mm_magic_t::tick
(
bool req_cmd_val,
bool req_cmd_store,
uint64_t req_cmd_addr,
uint64_t req_cmd_tag,
bool req_data_val,
void* req_data_bits,
bool resp_rdy
)
void mm_magic_t::tick(
bool ar_valid,
uint64_t ar_addr,
uint64_t ar_id,
uint64_t ar_size,
uint64_t ar_len,
bool aw_valid,
uint64_t aw_addr,
uint64_t aw_id,
uint64_t aw_size,
uint64_t aw_len,
bool w_valid,
uint64_t w_strb,
void *w_data,
bool w_last,
bool r_ready,
bool b_ready)
{
bool req_cmd_fire = req_cmd_val && req_cmd_ready();
bool req_data_fire = req_data_val && req_data_ready();
bool resp_fire = resp_valid() && resp_rdy;
assert(!(req_cmd_fire && req_data_fire));
bool ar_fire = ar_valid && ar_ready();
bool aw_fire = aw_valid && aw_ready();
bool w_fire = w_valid && w_ready();
bool r_fire = r_valid() && r_ready;
bool b_fire = b_valid() && b_ready;
if (resp_fire)
resp.pop();
if (ar_fire) {
uint64_t word_size = (1 << ar_size);
for (int i = 0; i <= ar_len; i++) {
auto dat = read(ar_addr + i * word_size, word_size);
rresp.push(mm_rresp_t(ar_id, dat, i == ar_len));
}
}
if (req_data_fire)
{
memcpy(data + store_addr + store_count*word_size, req_data_bits, word_size);
if (aw_fire) {
store_addr = aw_addr;
store_size = (1 << aw_size);
store_id = aw_id;
store_inflight = true;
store_count = aw_len + 1;
}
store_count = (store_count + 1) % (line_size/word_size);
if (store_count == 0)
if (w_fire) {
write(store_addr, (uint8_t *) w_data, w_strb, store_size);
store_addr += store_size;
store_count--;
if (store_count == 0) {
store_inflight = false;
}
if (req_cmd_fire)
{
auto byte_addr = req_cmd_addr * line_size;
assert(byte_addr < size);
if (req_cmd_store)
{
store_inflight = true;
store_addr = byte_addr;
}
else for (int i = 0; i < line_size/word_size; i++)
{
auto base = data + byte_addr + i*word_size;
auto dat = std::vector<char>(base, base + word_size);
resp.push(std::make_pair(req_cmd_tag, dat));
bresp.push(store_id);
assert(w_last);
}
}
if (b_fire)
bresp.pop();
if (r_fire)
rresp.pop();
cycle++;
}

122
csrc/mm.h
View File

@ -10,6 +10,9 @@
const int LINE_SIZE = 64; // all cores assume this.
const size_t MEM_SIZE = 1L * 1024*1024*1024;
void write_masked_data(
uint8_t *base, uint8_t *data, uint64_t strb, uint64_t size);
class mm_t
{
public:
@ -17,21 +20,39 @@ class mm_t
virtual void init(size_t sz, int word_size, int line_size);
virtual bool req_cmd_ready() = 0;
virtual bool req_data_ready() = 0;
virtual bool resp_valid() = 0;
virtual uint64_t resp_tag() = 0;
virtual void* resp_data() = 0;
virtual bool ar_ready() = 0;
virtual bool aw_ready() = 0;
virtual bool w_ready() = 0;
virtual bool b_valid() = 0;
virtual uint64_t b_resp() = 0;
virtual uint64_t b_id() = 0;
virtual bool r_valid() = 0;
virtual uint64_t r_resp() = 0;
virtual uint64_t r_id() = 0;
virtual void *r_data() = 0;
virtual bool r_last() = 0;
virtual void tick
(
bool req_cmd_val,
bool req_cmd_store,
uint64_t req_cmd_addr,
uint64_t req_cmd_tag,
bool req_data_val,
void* req_data_bits,
bool resp_rdy
bool ar_valid,
uint64_t ar_addr,
uint64_t ar_id,
uint64_t ar_size,
uint64_t ar_len,
bool aw_valid,
uint64_t aw_addr,
uint64_t aw_id,
uint64_t aw_size,
uint64_t aw_len,
bool w_valid,
uint64_t w_strb,
void *w_data,
bool w_last,
bool r_ready,
bool b_ready
) = 0;
virtual void* get_data() { return data; }
@ -39,47 +60,92 @@ class mm_t
virtual size_t get_word_size() { return word_size; }
virtual size_t get_line_size() { return line_size; }
void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size);
std::vector<char> read(uint64_t addr, uint64_t size);
virtual ~mm_t();
protected:
char* data;
uint8_t* data;
size_t size;
int word_size;
int line_size;
};
struct mm_rresp_t
{
uint64_t id;
std::vector<char> data;
bool last;
mm_rresp_t(uint64_t id, std::vector<char> data, bool last)
{
this->id = id;
this->data = data;
this->last = last;
}
mm_rresp_t()
{
this->id = 0;
this->last = false;
}
};
class mm_magic_t : public mm_t
{
public:
mm_magic_t() : store_inflight(false), store_count(0) {}
mm_magic_t() : store_inflight(false) {}
virtual void init(size_t sz, int word_size, int line_size);
virtual bool req_cmd_ready() { return !store_inflight; }
virtual bool req_data_ready() { return store_inflight; }
virtual bool resp_valid() { return !resp.empty(); }
virtual uint64_t resp_tag() { return resp_valid() ? resp.front().first : 0; }
virtual void* resp_data() { return resp_valid() ? &resp.front().second[0] : &dummy_data[0]; }
virtual bool ar_ready() { return true; }
virtual bool aw_ready() { return !store_inflight; }
virtual bool w_ready() { return store_inflight; }
virtual bool b_valid() { return !bresp.empty(); }
virtual uint64_t b_resp() { return 0; }
virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; }
virtual bool r_valid() { return !rresp.empty(); }
virtual uint64_t r_resp() { return 0; }
virtual uint64_t r_id() { return r_valid() ? rresp.front().id: 0; }
virtual void *r_data() { return r_valid() ? &rresp.front().data[0] : &dummy_data[0]; }
virtual bool r_last() { return r_valid() ? rresp.front().last : false; }
virtual void tick
(
bool req_cmd_val,
bool req_cmd_store,
uint64_t req_cmd_addr,
uint64_t req_cmd_tag,
bool req_data_val,
void* req_data_bits,
bool resp_rdy
bool ar_valid,
uint64_t ar_addr,
uint64_t ar_id,
uint64_t ar_size,
uint64_t ar_len,
bool aw_valid,
uint64_t aw_addr,
uint64_t aw_id,
uint64_t aw_size,
uint64_t aw_len,
bool w_valid,
uint64_t w_strb,
void *w_data,
bool w_last,
bool r_ready,
bool b_ready
);
protected:
bool store_inflight;
int store_count;
uint64_t store_addr;
uint64_t store_id;
uint64_t store_size;
uint64_t store_count;
std::vector<char> dummy_data;
std::queue<uint64_t> bresp;
std::queue<mm_rresp_t> rresp;
uint64_t cycle;
std::queue<std::pair<uint64_t, std::vector<char>>> resp;
};
void load_mem(void* mem, const char* fn);

122
csrc/mm_dramsim2.cc
View File

@ -17,27 +17,17 @@ using namespace DRAMSim;
void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
{
assert(req.count(address));
auto tag = req[address];
req.erase(address);
for (int i = 0; i < line_size/word_size; i++)
{
auto base = data + address + i*word_size;
auto dat = std::vector<char>(base, base + word_size);
resp.push(std::make_pair(tag, dat));
auto req = rreq[address];
for (int i = 0; i < req.len; i++) {
auto dat = read(address + i * req.size, req.size);
rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1)));
}
#ifdef DEBUG_DRAMSIM2
fprintf(stderr, "[Callback] read complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
#endif
}
void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
{
#ifdef DEBUG_DRAMSIM2
fprintf(stderr, "[Callback] write complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
#endif
auto b_id = wreq[address];
bresp.push(b_id);
}
void power_callback(double a, double b, double c, double d)
@ -64,65 +54,65 @@ void mm_dramsim2_t::init(size_t sz, int wsz, int lsz)
#endif
}
void mm_dramsim2_t::tick
(
bool req_cmd_val,
bool req_cmd_store,
uint64_t req_cmd_addr,
uint64_t req_cmd_tag,
bool req_data_val,
void* req_data_bits,
bool resp_rdy
)
void mm_dramsim2_t::tick(
bool ar_valid,
uint64_t ar_addr,
uint64_t ar_id,
uint64_t ar_size,
uint64_t ar_len,
bool aw_valid,
uint64_t aw_addr,
uint64_t aw_id,
uint64_t aw_size,
uint64_t aw_len,
bool w_valid,
uint64_t w_strb,
void *w_data,
bool w_last,
bool r_ready,
bool b_ready)
{
bool req_cmd_fire = req_cmd_val && req_cmd_ready();
bool req_data_fire = req_data_val && req_data_ready();
bool resp_fire = resp_valid() && resp_rdy;
assert(!(req_cmd_fire && req_data_fire));
bool ar_fire = ar_valid && ar_ready();
bool aw_fire = aw_valid && aw_ready();
bool w_fire = w_valid && w_ready();
bool r_fire = r_valid() && r_ready;
bool b_fire = b_valid() && b_ready;
if (resp_fire)
resp.pop();
if (req_cmd_fire)
{
// since the I$ can speculatively ask for address that are out of bounds
auto byte_addr = (req_cmd_addr * line_size) % size;
if (req_cmd_store)
{
store_inflight = 1;
store_addr = byte_addr;
#ifdef DEBUG_DRAMSIM2
fprintf(stderr, "Starting store transaction (addr=%lx ; tag=%ld ; cyc=%ld)\n", store_addr, req_cmd_tag, cycle);
#endif
}
else
{
assert(!req.count(byte_addr));
req[byte_addr] = req_cmd_tag;
mem->addTransaction(false, byte_addr);
#ifdef DEBUG_DRAMSIM2
fprintf(stderr, "Adding load transaction (addr=%lx; cyc=%ld)\n", byte_addr, cycle);
#endif
}
if (ar_fire) {
rreq[ar_addr] = mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr);
mem->addTransaction(false, ar_addr);
}
if (req_data_fire)
{
memcpy(data + store_addr + store_count*word_size, req_data_bits, word_size);
if (aw_fire) {
store_addr = aw_addr;
store_size = (1 << aw_size);
store_id = aw_id;
store_count = aw_len + 1;
store_inflight = true;
}
store_count = (store_count + 1) % (line_size/word_size);
if (store_count == 0)
{ // last chunch of cache line arrived.
store_inflight = 0;
if (w_fire) {
write(store_addr, (uint8_t *) w_data, w_strb, store_size);
store_addr += store_size;
store_count--;
if (store_count == 0) {
store_inflight = false;
mem->addTransaction(true, store_addr);
#ifdef DEBUG_DRAMSIM2
fprintf(stderr, "Adding store transaction (addr=%lx; cyc=%ld)\n", store_addr, cycle);
#endif
wreq[store_addr] = store_id;
assert(w_last);
}
}
if (b_fire)
bresp.pop();
if (r_fire)
rresp.pop();
mem->update();
cycle++;
}

77
csrc/mm_dramsim2.h
View File

@ -9,28 +9,69 @@
#include <queue>
#include <stdint.h>
struct mm_req_t {
uint64_t id;
uint64_t size;
uint64_t len;
uint64_t addr;
mm_req_t(uint64_t id, uint64_t size, uint64_t len, uint64_t addr)
{
this->id = id;
this->size = size;
this->len = len;
this->addr = addr;
}
mm_req_t()
{
this->id = 0;
this->size = 0;
this->len = 0;
this->addr = 0;
}
};
class mm_dramsim2_t : public mm_t
{
public:
mm_dramsim2_t() : store_inflight(false), store_count(0) {}
mm_dramsim2_t() : store_inflight(false) {}
virtual void init(size_t sz, int word_size, int line_size);
virtual bool req_cmd_ready() { return mem->willAcceptTransaction() && !store_inflight; }
virtual bool req_data_ready() { return mem->willAcceptTransaction() && store_inflight; }
virtual bool resp_valid() { return !resp.empty(); }
virtual uint64_t resp_tag() { return resp_valid() ? resp.front().first : 0; }
virtual void* resp_data() { return resp_valid() ? &resp.front().second[0] : &dummy_data[0]; }
virtual bool ar_ready() { return mem->willAcceptTransaction(); }
virtual bool aw_ready() { return mem->willAcceptTransaction() && !store_inflight; }
virtual bool w_ready() { return store_inflight; }
virtual bool b_valid() { return !bresp.empty(); }
virtual uint64_t b_resp() { return 0; }
virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; }
virtual bool r_valid() { return !rresp.empty(); }
virtual uint64_t r_resp() { return 0; }
virtual uint64_t r_id() { return r_valid() ? rresp.front().id: 0; }
virtual void *r_data() { return r_valid() ? &rresp.front().data[0] : &dummy_data[0]; }
virtual bool r_last() { return r_valid() ? rresp.front().last : false; }
virtual void tick
(
bool req_cmd_val,
bool req_cmd_store,
uint64_t req_cmd_addr,
uint64_t req_cmd_tag,
bool req_data_val,
void* req_data_bits,
bool resp_rdy
bool ar_valid,
uint64_t ar_addr,
uint64_t ar_id,
uint64_t ar_size,
uint64_t ar_len,
bool aw_valid,
uint64_t aw_addr,
uint64_t aw_id,
uint64_t aw_size,
uint64_t aw_len,
bool w_valid,
uint64_t w_strb,
void *w_data,
bool w_last,
bool r_ready,
bool b_ready
);
@ -39,12 +80,16 @@ class mm_dramsim2_t : public mm_t
uint64_t cycle;
bool store_inflight;
int store_count;
uint64_t store_addr;
uint64_t store_id;
uint64_t store_size;
uint64_t store_count;
std::vector<char> dummy_data;
std::queue<uint64_t> bresp;
std::map<uint64_t, uint64_t> wreq;
std::map<uint64_t,uint64_t> req;
std::queue<std::pair<uint64_t, std::vector<char>>> resp;
std::map<uint64_t, mm_req_t> rreq;
std::queue<mm_rresp_t> rresp;
void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
void write_complete(unsigned id, uint64_t address, uint64_t clock_cycle);

101
csrc/vcs_main.cc
View File

@ -48,50 +48,95 @@ int main(int argc, char** argv)
}
void memory_tick(
vc_handle mem_req_val,
vc_handle mem_req_rdy,
vc_handle mem_req_store,
vc_handle mem_req_addr,
vc_handle mem_req_tag,
vc_handle ar_valid,
vc_handle ar_ready,
vc_handle ar_addr,
vc_handle ar_id,
vc_handle ar_size,
vc_handle ar_len,
vc_handle mem_req_data_val,
vc_handle mem_req_data_rdy,
vc_handle mem_req_data_bits,
vc_handle aw_valid,
vc_handle aw_ready,
vc_handle aw_addr,
vc_handle aw_id,
vc_handle aw_size,
vc_handle aw_len,
vc_handle mem_resp_val,
vc_handle mem_resp_rdy,
vc_handle mem_resp_tag,
vc_handle mem_resp_data)
vc_handle w_valid,
vc_handle w_ready,
vc_handle w_strb,
vc_handle w_data,
vc_handle w_last,
vc_handle r_valid,
vc_handle r_ready,
vc_handle r_resp,
vc_handle r_id,
vc_handle r_data,
vc_handle r_last,
vc_handle b_valid,
vc_handle b_ready,
vc_handle b_resp,
vc_handle b_id)
{
uint32_t req_data[mm->get_word_size()/sizeof(uint32_t)];
uint32_t write_data[mm->get_word_size()/sizeof(uint32_t)];
for (size_t i = 0; i < mm->get_word_size()/sizeof(uint32_t); i++)
req_data[i] = vc_4stVectorRef(mem_req_data_bits)[i].d;
write_data[i] = vc_4stVectorRef(w_data)[i].d;
vc_putScalar(mem_req_rdy, mm->req_cmd_ready());
vc_putScalar(mem_req_data_rdy, mm->req_data_ready());
vc_putScalar(mem_resp_val, mm->resp_valid());
vc_putScalar(ar_ready, mm->ar_ready());
vc_putScalar(aw_ready, mm->aw_ready());
vc_putScalar(w_ready, mm->w_ready());
vc_putScalar(b_valid, mm->b_valid());
vc_putScalar(r_valid, mm->r_valid());
vc_putScalar(r_last, mm->r_last());
vec32 d[mm->get_word_size()/sizeof(uint32_t)];
d[0].c = 0;
d[0].d = mm->resp_tag();
vc_put4stVector(mem_resp_tag, d);
d[0].d = mm->b_resp();
vc_put4stVector(b_resp, d);
d[0].c = 0;
d[0].d = mm->b_id();
vc_put4stVector(b_id, d);
d[0].c = 0;
d[0].d = mm->r_resp();
vc_put4stVector(r_resp, d);
d[0].c = 0;
d[0].d = mm->r_id();
vc_put4stVector(r_id, d);
for (size_t i = 0; i < mm->get_word_size()/sizeof(uint32_t); i++)
{
d[i].c = 0;
d[i].d = ((uint32_t*)mm->resp_data())[i];
d[i].d = ((uint32_t*)mm->r_data())[i];
}
vc_put4stVector(mem_resp_data, d);
vc_put4stVector(r_data, d);
mm->tick
(
vc_getScalar(mem_req_val),
vc_getScalar(mem_req_store),
vc_4stVectorRef(mem_req_addr)->d,
vc_4stVectorRef(mem_req_tag)->d,
vc_getScalar(mem_req_data_val),
req_data,
vc_getScalar(mem_resp_rdy)
vc_getScalar(ar_valid),
vc_4stVectorRef(ar_addr)->d,
vc_4stVectorRef(ar_id)->d,
vc_4stVectorRef(ar_size)->d,
vc_4stVectorRef(ar_len)->d,
vc_getScalar(aw_valid),
vc_4stVectorRef(aw_addr)->d,
vc_4stVectorRef(aw_id)->d,
vc_4stVectorRef(aw_size)->d,
vc_4stVectorRef(aw_len)->d,
vc_getScalar(w_valid),
vc_4stVectorRef(w_strb)->d,
write_data,
vc_getScalar(w_last),
vc_getScalar(r_ready),
vc_getScalar(b_ready)
);
}