riscv/rocket-chip
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96 Commits

Author SHA1 Message Date
Wesley W. Terpstra
93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Jim Lawson
3c1dac8c68 Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. (#526) 
This anticipates ucb-bar/chisel3#448. When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.
 2017-01-26 11:11:14 -08:00
Wesley W. Terpstra
e8e95d4bcf regression: remove cde submodule update 2016-11-23 10:28:22 -08:00
Andrew Waterman
f8bb67ab8f Bind some Make vars early to avoid redundant evaluation 2016-10-28 11:56:13 -07:00
Andrew Waterman
2b65478f3a bump chisel/firrtl 2016-10-28 00:36:53 -07:00
Henry Cook
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Scott Beamer
f7121a2a5b support for BSD sed (GNU sed still works) 2016-09-14 12:21:39 -07:00
Howard Mao
08089f695d allow configuration to be in separate project from test harness 2016-09-01 10:28:07 -07:00
Howard Mao
eba692786b make sure FIRRTL jar gets updated timestamp 2016-08-19 13:45:23 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
a756856d84 make sure coreplex sources included in make dependencies 2016-08-11 14:27:03 -07:00
Howard Mao
163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Palmer Dabbelt
dab96096b4 Add firrtl build dependencies 
Without this when I update firrtl the new version doesn't get built, so
my build is constantly failing.
 2016-08-05 14:45:00 -07:00
Howard Mao
b30e0254ee fix Makefrag to detect all Chisel source files 2016-06-28 16:39:10 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Howard Mao
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
Palmer Dabbelt
68ba33369b Default to Chisel 3 
Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
 2016-06-15 14:01:43 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Yunsup Lee
4afc9c69a0 streamline sbt 2016-04-19 14:22:22 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Howard Mao
85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
Palmer Dabbelt
95b065153d Add CDE to the submodule list 
Without this I don't get rebuilds when toching a file in CDE.
 2016-02-17 15:23:25 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Palmer Dabbelt
1149a412cc Support make-3.82 and newer 
make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests".  This patch changes the hex file
rules to ensure they match between the two versions of make.

I've tried this with both make-3.81 and make-4.1, and they both work for me.
 2016-01-28 12:19:11 -08:00
Jim Lawson
c5e9558571 Double Java MaxPermSize. 2015-12-07 12:05:06 -08:00
Howard Mao
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Colin Schmidt
6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild 2015-09-16 12:28:03 -07:00
Ben Keller
8e9c15c10d If you don't have spike-disasm in your path, your path is dumped 
to stdout by this line every time you do anything in the entire repo.
 2015-09-03 15:36:11 -07:00
Scott Beamer
333c594d2a respect environment's CXX 2015-08-25 13:26:14 -07:00
Andrew Waterman
34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Henry Cook
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). 
Bump all submodules.
 2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Henry Cook
866396545d For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten 2015-07-23 17:00:22 -07:00
Yunsup Lee
caf89baeb7 update zscale 2015-07-23 13:59:45 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Yunsup Lee
d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Yunsup Lee
09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00