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Write test harness in Chisel

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This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
This commit is contained in:
Andrew Waterman
2016-08-15 22:03:03 -07:00
parent 2d1d7266f5
commit ed827678ac
38 changed files with 483 additions and 1792 deletions
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23
Makefrag
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@ -3,14 +3,11 @@ ifndef RISCV
$(error Please set environment variable RISCV. Please take a look at README)
endif
MODEL ?= Top
MODEL ?= TestHarness
PROJECT := rocketchip
CXX ?= g++
CXXFLAGS := -O1
CHISEL_VERSION ?= 3
export CHISEL_VERSION
SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar
SHELL := /bin/bash
@ -20,11 +17,7 @@ FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Drive
$(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala")
$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
ifeq ($(CHISEL_VERSION),2)
CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
else
CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
endif
CHISEL_ARGS := --targetDir $(generated_dir)
src_path = src/main/scala
default_submodules = . junctions uncore hardfloat rocket groundtest coreplex context-dependent-environments
@ -41,16 +34,6 @@ timeout_cycles = 100000000
bootrom_img = $(base_dir)/bootrom/bootrom.img
#--------------------------------------------------------------------
# DRAMSim2
#--------------------------------------------------------------------
DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(base_dir)/dramsim2/*.cpp))
$(DRAMSIM_OBJS): %.o: %.cpp
$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
$(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
ar rcs $@ $^
#--------------------------------------------------------------------
# Build Tests
#--------------------------------------------------------------------
@ -71,7 +54,6 @@ $(consts_header): $(params_file)
echo "#ifndef __CONST_H__" > $@
echo "#define __CONST_H__" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@
echo "#endif // __CONST_H__" >> $@
params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm
@ -80,7 +62,6 @@ $(consts_header_debug): $(params_file_debug)
echo "#ifndef __CONST_H__" > $@
echo "#define __CONST_H__" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@
echo "#endif // __CONST_H__" >> $@
clean-run-output: